Generic TDD Engine #975
Generic TDD Engine #975
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The Guideline checker action for this PR will fail because SystemVerilog files are not fully supported, for example packages. |
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The IP looks great, however since it is not pin compatible with the old IP the project which use is will fail. Example projects/ad9081_fmca_ebz/zcu102 when compiled with the following parameters:
make TDD_SUPPORT=1 SHARED_DEVCLK=1
Ideally this commit should go to master only when the above project is updated.
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v1.1: Minor update in axi_tdd_channel.sv to change the reset value of ch_pol to DEFAULT_POLARITY. |
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V2
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v2.1: Added the TDD regmap files. |
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v2.2: Integrated the new TDD engine in the ad9081_fmca_ebz_x_band project. |
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v2.3: Updated the scripts to create a wrapper around the TDD core and generated channel slices. |
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Replaced the existing axi_tdd with the new version * Added DEFAULT_POLARITY synth parameter and RO register * Added TDD_STATUS register * Added TDD_SYNC_RST feature * Used the asy_ prefix for signals which are not synced * Added logic to force the state from ARMED to RUNNING when startup_delay=0 * Added feature to finish the burst when the module is disabled before its completion Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Replaces the existing axi_tdd with the new version