PlutoSDR: Prepare for v0.24 release

Submodule linux 01a3695..7d66120:
  > arm: dts: zynq-zed-adf7242.dts: Add
  > net: ieee802154: adf7242: Rework IRQ and packet handling
  > net: ieee802154: adf7242: Avoid redundant RC_READY polling
  > net: ieee802154: adf7242: Add additional DEBUG information
  > net: ieee802154: adf7242: Fix bug if defined DEBUG
  > net: ieee802154: adf7242: Add support for ADF7241 devices
  > ieee802154: adf7242: use unsigned int over only unsigned
  > net: ieee802154: constify ieee802154_ops structures
  > iio: ad9467: Don't write 'register transfer' register for AD9680 and similar
  > iio: ad9467: ad9680_setup(): Remove unused parameters
  > iio: ad9647: ad9680: Don't write data format register during initial setup
  > iio: ad9467: ad9680: Don't set test mode during initial setup
  > iio: ad9467: Make AD9680 sfdr_optim_regs static
  > iio: ad9467: Fix AD9684 input full-scale range selection
  > iio: ad9467: Remove trailing space from available attributes
  > iio: ad9467: Handle scale values >= 1.0
  > iio: ad9467: Factor input range handling into separate helper functions
  > iio: ad9467: Fix available test modes for newer generation devices
  > iio: ad9467: Fix ad9680 input range reading
  > iio: ad9467: Fix max_testmode for AD9434
  > iio: adc: ad9361: Fix MGC decrement gain step size
  > iio: ad9528: Make ID register read 3 bytes
  > iio: adc: cf_axi_adc_core: only register buffer if dmas node is present
  > drivers/iio/industrialio-core: Fix error introduced in previous commit
  > iio: ad9361: Add *_available RANGE attributes
  > iio:core: add a callback to allow drivers to provide _available attributes
  > dma: axi-dmac: Infer synthesis configuration parameters hardware
  > iio: adc: ad9361: Fix compiler warnings
  > arm64: dts: /xilinx/zynqmp-zcu102-rev10-fmcdaq2: Add dt for DAQ2 on ZCU102
  > arm: dts: zynq-pluto-sdr-revc.dts: Add PlutoSDR Rev.C
  > iio: adc: cf_axi_adc_core: Fix possible SLAVE device remove bug
  > arm64: dts: xilinx/zynqmp-zcu102-rev10-ad9364-fmcomms4.dts: Add
  > arm64: configs: adi_zynqmp_defconfig: Update
  > arm64: dts: xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dts: Add
  > Merge branch '2017_R1' into xcomm_zynq
  > dts: zynq-*-ad936*-*.dts: DMAC switch to new dt bindings
  > Merge branch 'xcomm_zynq' of https://github.com/analogdevicesinc/linux into xcomm_zynq
  > char: xilinx_devcfg: Fix regression introduced in remove volatile commmit

  Submodule buildroot 0a4e137..9766671:
  > package/libiio/libiio.mk: Push to version 0.11

  Submodule hdl 06bab87..3e565bc:
  > fmcadc5: Disable constraints for jesd sysref in order to remove critical warning
  > axi_dmac: Align the data_ready to data
  > daq2_zcu102: Fix typo
  > Require Vivado 2017.2.1 for all zcu102 projects
  > adrv9371x_zcu102: Fix rx_div_clk constraint placement
  > fmcadc5: Update make
  > fmcadc5: Update to the ADI JESD interface
  > Make: Update makefiles
  > library: Update
  > daq2, daq3: zcu102: Update constraints
  > daq2: Set correct transceiver type for UltraScale projects
  > adrv9371x: Set correct transceiver type for UltraScale projects
  > axi_adxcvr: Correctly report the transceiver type in the register map
  > adrv9371x: zcu102: Fix lane mapping
  > adrv9371x: zcu102: Fix QPLL feedback divider
  > fmcjesdadc1: Update A10GX/A10SOC projects to the ADI JESD framework
  > zcu102 constraints description/cosmetic updates
  > zcu102: Update to rev 1.0
  > fmcomms2: Connect dac data underflow
  > axi_dmac: Reset fifo_rd_data without delaying the valid data
  > avl_dacfifo: Fix dac_xfer_req generation
  > avl_dacfifo: Fix reset architecture in avl_dacfifo_rd
  > avl_dacfifo: Fix the loopback of avl_xfer_req
  > avl_dacfifo: Fix write enable generation
  > avl_dacfifo: Fix reset of write address register
  > daq3: Disable start synchronization for the ADC DMA
  > daq2: Disable start synchronization for the ADC DMA
  > avl_dacfifo: Refactor the fifo
  > daq2/zcu102: Pin Swap for ZCU102 Rev1.0
  > daq3: A10GX, overconstrained failing paths
  > daq3: A10GX, updated to the ADI JESD204
  > jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps
  > daq2: A10GX, added additional interconnect pipelining
  > adi_env: Normalize environment variables
  > adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing
  > daq2: A10GX, added extra pipelining in the interconnect in order to improve timing
  > daq2: A10GX, connect dac_fifo_bypass to gpio
  > daq2: A10SOC, added dac fifo
  > daq2: A10GX, added dac fifo
  > axi_ad9361: Fix dac_datarate counter implementation

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>