Register Names

[af4815162342]

Hi

I see that pyvex attempts to name registers, e.g., on x86, an offset of 8 into VexGuestX86State means it will be called eax. However, this might lead to some confusion because an instruction like mov al, 3 is represented as PUT(eax) = 0x03 in pyvex, which might be misinterpreted.
I think it would be better if the size of the source was taken into account and, depending on this and the offset, the register is named more accurately, i.e., in this case PUT(al) = 0x03. I also noticed that bytes 8-15 do not get a name at all (ah, bh, ch, dh) and are represented as, e.g., PUT(9) = 0x03.

Cheers!

[rhelmot]

I was the one who implemented the register name stuff in the first place since I got sick of the default IR having just offsets, and I intentionally skipped these cases since I thought they would be too complicated to cover correctly, but I'm looking over the code right now and it shouldn't be too hard, just adding a size parameter to archinfo.Arch.translate_register_name(), since all that information is accessible from the GET and PUT expressions, either in the GET's type information or the PUT's expression's type information.

I'll get around to this eventually for sure, but if you want it faster we will gladly accept pull requests :)

[rhelmot]

This is implemented in 0c99973!