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A tiny Open POWER ISA softcore written in VHDL 2008
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antonblanchard Merge pull request #57 from antonblanchard/add-nop
Add a decode for the nop instruction
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fpga SOC memory wishbone should clear ACK regardless of STB Sep 12, 2019
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scripts Fix verific script with new VHDL files Sep 6, 2019
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.travis.yml Allow a full make check on Travis Sep 11, 2019
LICENSE Initial import of microwatt Aug 22, 2019
Makefile Add a simple direct mapped icache Sep 12, 2019
README.md Add pretty gif demo of MicroPython on Microwatt to README.md Aug 27, 2019
common.vhdl Add a simple direct mapped icache Sep 12, 2019
core.vhdl Add a simple direct mapped icache Sep 12, 2019
core_tb.vhdl Add a simple direct mapped icache Sep 12, 2019
cr_file.vhdl Fix CR forwarding Sep 9, 2019
crhelpers.vhdl Initial import of microwatt Aug 22, 2019
decode1.vhdl Add a decode for the nop instruction Sep 15, 2019
decode2.vhdl Merge pull request #47 from antonblanchard/if-fix Sep 11, 2019
decode_types.vhdl Add a decode for the nop instruction Sep 15, 2019
execute1.vhdl Remove FIXME comment Sep 11, 2019
execute2.vhdl Fix issue in execute2 Sep 11, 2019
fetch1.vhdl Add a default value for RESET_ADDRESS Sep 15, 2019
fetch2.vhdl Add a simple direct mapped icache Sep 12, 2019
glibc_random.vhdl Initial import of microwatt Aug 22, 2019
glibc_random_helpers.vhdl Initial import of microwatt Aug 22, 2019
helpers.vhdl Remove dynamic ranges from code Aug 30, 2019
icache.vhdl Add a simple direct mapped icache Sep 12, 2019
insn_helpers.vhdl Rework decode2 Sep 3, 2019
loadstore1.vhdl Fix issue in loadstore1 Sep 11, 2019
loadstore2.vhdl Remove second write port Sep 9, 2019
microwatt.core Add a simple direct mapped icache Sep 12, 2019
multiply.vhdl Reduce multiply to 2 cycles Sep 11, 2019
multiply_tb.vhdl Initial import of microwatt Aug 22, 2019
ppc_fx_insns.vhdl Remove dynamic ranges from code Aug 30, 2019
register_file.vhdl Add forwarding in the register file Sep 9, 2019
sim_console.vhdl Initial import of microwatt Aug 22, 2019
sim_console_c.c Make sim poll non-blocking Sep 9, 2019
sim_uart.vhdl Share soc.vhdl between FPGA and sim Sep 10, 2019
simple_ram_behavioural.vhdl Share soc.vhdl between FPGA and sim Sep 10, 2019
simple_ram_behavioural_helpers.vhdl Initial import of microwatt Aug 22, 2019
simple_ram_behavioural_helpers_c.c Silence some loadstore related debug Sep 9, 2019
simple_ram_behavioural_tb.bin Initial import of microwatt Aug 22, 2019
simple_ram_behavioural_tb.vhdl Share soc.vhdl between FPGA and sim Sep 10, 2019
soc.vhdl Switch soc to use std_ulogic Sep 10, 2019
wishbone_arbiter.vhdl Initial import of microwatt Aug 22, 2019
wishbone_types.vhdl Remove names from end record statements Sep 11, 2019
writeback.vhdl Reformat writeback.vhdl Sep 14, 2019

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • Need to implement a simple non pipelined divide
  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)
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