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Some VHDL compilers like verific [1] don't like these, so let's remove them. Lots of random code changes, but passes make check. Also add basic script to run verific and generate verilog. 1. https://www.verific.com/ Signed-off-by: Michael Neuling <mikey@neuling.org>
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Original file line number | Diff line number | Diff line change |
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#!/bin/bash | ||
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D=$(dirname $0) | ||
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TCL=$(mktemp) | ||
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VERIFICDIR=$(dirname $(dirname $(which verific-linux))) | ||
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echo "setvhdllibrarypath -default $VERIFICDIR/vhdl_packages/vdbs_2008" >> $TCL | ||
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# FIXME: make this list dynamic | ||
for i in decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl fetch2.vhdl decode1.vhdl helpers.vhdl decode2.vhdl register_file.vhdl cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl sim_console.vhdl execute1.vhdl execute2.vhdl loadstore1.vhdl loadstore2.vhdl multiply.vhdl writeback.vhdl wishbone_arbiter.vhdl core.vhdl simple_ram_behavioural_helpers.vhdl simple_ram_behavioural.vhdl core_tb.vhdl; do | ||
F=$(realpath $D/../$i) | ||
echo "analyze -format vhdl -vhdl_2008 $F" >> $TCL | ||
done | ||
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echo "elaborate core" >> $TCL | ||
echo "write core.v" >> $TCL | ||
echo "area" >> $TCL | ||
echo "optimize -hierarchy -constant -cse -operator -dangling -resource" >> $TCL | ||
echo "area" >> $TCL | ||
echo "write core-optimised.v" >> $TCL | ||
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verific-linux -script_file $TCL | ||
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rm -rf $TCL |