arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro #6101
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pkarashchenko
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
no1wudi
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xiaoxiang781216
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Apr 20, 2022
Ouss4
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Summary
Merge status/fpu context save/load to save_ctx/load_ctx to improve performance (no jal instruction).
Impact
RISC-V
Testing
QEMU