arch/risc-v/riscv_misaligned: Implement float load/store support #6117
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pkarashchenko
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Apr 21, 2022
no1wudi
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pkarashchenko
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Apr 21, 2022
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
xiaoxiang781216
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Apr 22, 2022
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Summary
Implement misaligned float load/store
Impact
risc-v with FPU support
Testing
K210