mpfs: Add CoreSPI driver for Polarfire SoC

arch/risc-v/src/mpfs/Kconfig

@@ -439,6 +439,46 @@ config MPFS_ETHMAC_1
 	---help---
 		Enable MPFS ethernet MAC-1.
 
+config MPFS_HAVE_CORESPI
+	bool "CoreSPI FPGA IP block configured"
+	default n
+
+if MPFS_HAVE_CORESPI
+
+config MPFS_CORESPI
+	bool "CoreSPI FPGA IP block configured"
+	default n
+	depends on MPFS_HAVE_CORESPI
+
+config MPFS_CORESPI_BASE
+	hex "Base address for the (first) CoreSPI instance"
+	default 0x4B008000
+	depends on MPFS_CORESPI
+
+config MPFS_CORESPI_INST_OFFSET
+	hex "Offset of instances in memory, base + n * offset finds instance n"
+	default 0x1000
+	depends on MPFS_CORESPI
+
+config MPFS_CORESPI_INSTANCES
+	int "Amount of CoreSPI instances"
+	default 1
+	range 1 8
+	depends on MPFS_CORESPI
+
+config MPFS_CORESPI_IRQNUM
+	int "Number of (first) F2H interrupt"
+	default 20
+	range 0 63
+	depends on MPFS_CORESPI
+
+config MPFS_CORESPI_IRQNUM_OFFSET
+	int "Offset of interrupt source for instance n"
+	default 1
+	depends on MPFS_CORESPI
+
+endif # MPFS_HAVE_CORESPI
+
 comment "CorePWM Options"
 
 config MPFS_HAVE_COREPWM

arch/risc-v/src/mpfs/Make.defs

@@ -94,3 +94,8 @@ endif
 ifeq ($(CONFIG_MPFS_IHC_SBI),y)
 CHIP_CSRCS += mpfs_ihc_sbi.c
 endif
+
+ifeq ($(CONFIG_MPFS_CORESPI),y)
+CHIP_CSRCS += mpfs_corespi.c
+endif
+

arch/risc-v/src/mpfs/hardware/mpfs_corespi.h

@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/risc-v/src/mpfs/hardware/mpfs_corespi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_CORESPI_H
+#define __ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_CORESPI_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* CONTROL register */
+
+#define MPFS_SPI_OENOFF               (1 << 7)
+#define MPFS_SPI_FRAMEURUN            (1 << 6)
+#define MPFS_SPI_INTTXTURUN           (1 << 5)
+#define MPFS_SPI_INTRXOVRFLOW         (1 << 4)
+#define MPFS_SPI_INTTXDONE            (1 << 3)
+#define MPFS_SPI_MODE                 (1 << 1)
+#define MPFS_SPI_ENABLE               (1 << 0)
+
+/* INT_CLEAR/RAW/MASK register */
+
+#define MPFS_SPI_TXRFM                (1 << 7)
+#define MPFS_SPI_DATA_RX              (1 << 6)
+#define MPFS_SPI_SSEND                (1 << 5)
+#define MPFS_SPI_CMDINT               (1 << 4)
+#define MPFS_SPI_TXCHUNDRUN           (1 << 3)
+#define MPFS_SPI_RXCHOVRFLW           (1 << 2)
+#define MPFS_SPI_TXDONE               (1 << 0)
+
+/* STATUS register */
+
+#define MPFS_SPI_ACTIVE               (1 << 7)
+#define MPFS_SPI_SSEL                 (1 << 6)
+#define MPFS_SPI_TXUNDERRUN           (1 << 5)
+#define MPFS_SPI_RXOVERFLOW           (1 << 4)
+#define MPFS_SPI_TXFULL               (1 << 3)
+#define MPFS_SPI_RXEMPTY              (1 << 2)
+#define MPFS_SPI_DONE                 (1 << 1)
+#define MPFS_SPI_FIRSTFRAME           (1 << 0)
+
+/* CONTROL2 register */
+
+#define MPFS_SPI_INTEN_TXFRM          (1 << 7)
+#define MPFS_SPI_INTEN_DATA_RX        (1 << 6)
+#define MPFS_SPI_INTEN_SSEND          (1 << 5)
+#define MPFS_SPI_INTEN_CMD            (1 << 4)
+#define MPFS_SPI_CMDSIZE_MASK         (7 << 0)
+#define MPFS_SPI_CMDSIZE_SHIFT        (1)
+
+/* COMMAND register */
+
+#define MPFS_SPI_TXFIFORST            (1 << 1)
+#define MPFS_SPI_RXFIFORST            (1 << 0)
+
+#endif /* __ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_CORESPI_H */