mpfs: Add CoreSPI driver for Polarfire SoC #9439
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Thanks for looking into this, the style errors are now fixed as well as the modifyreg silliness |
Adds a driver for an FPGA fabric / CoreSPI implementation. Supports multiple instances, assuming they reside in some base address, offsettable by a constant value.
Also change the defaults
…STANCES macro Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The logic for rx_fifo_empty is wrong, needs a loop for the retry to work
Remove unnecessary reading of the status register when loading / unloading the FIFOs. Reading from the IP block is slow due to BUS synchronization and this basically makes the SPI busy loop for no reason at all, destroying the CPU usage. The overall benefit of these changes is approx. 25%-points, which is a MASSIVE improvement.
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The rest of the style errors should now be fixed too |
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Summary
Add driver for CoreSPI https://www.microchip.com/en-us/products/fpgas-and-plds/ip-core-tools/corespi into NuttX. User can instantiate up to 8 instances. Driver assumes the instances live in contiguous memory locations and have contiguous interrupt numbers.
Impact
MPFS only, add new driver
Testing
icicle:nsh