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32-bit single core based implementation of RISC-V ISS feature specifications and covers all permitted configurations.

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RISC-V-Simulator

Overview

RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.
This is a 32-bit single core based implementation of RISC-V ISS feature specifications and covers all permitted configurations.

How to build

Build requirements

C++ compiler used in this project is, GNU G++14.

Build

git     clone   https://github.com/ar-pavel/RISC-V-Simulator.git
cd  RISC-V-Simulator
./make

Supported Operations

Operation templates that are supported by this simulator:

Usage Template           Type Description   Detailed Description          
add     rd, rs1, rs2 R Add rd ← rs1 + rs2, pc ← pc+4
addi     rd, rs1, imm I Add Immediate rd ← rs1 + imm i, pc ← pc+4
and     rd, rs1, rs2 R AND rd ← rs1 & rs2, pc ← pc+4
andi     rd, rs1, imm I AND Immediate rd ← rs1 & imm i, pc ← pc+4
auipc     rd, imm U Add Upper Immediate to PC rd ← pc + imm u, pc ← pc+4
beq     rs1, rs2, pcrel_13 B Branch Equal pc ← pc + ((rs1==rs2) ? imm b : 4)
bge     rs1, rs2, pcrel_13 B Branch Greater or Equal pc ← pc + ((rs1>=rs2) ? imm b : 4)
bgeu     rs1, rs2, pcrel_13 B Branch Greater or Equal Unsigned pc ← pc + ((rs1>=rs2) ? imm b : 4)
blt     rs1, rs2, pcrel_13 B Branch Less Than pc ← pc + ((rs1<rs2) ? imm b : 4)
bltu     rs1, rs2, pcrel_13 B Branch Less Than Unsigned pc ← pc + ((rs1<rs2) ? imm b : 4)
bne     rs1, rs2, pcrel_13 B Branch Not Equal pc ← pc + ((rs1!=rs2) ? imm b : 4)
jal       rd, pcrel_21 J Jump And Link rd ← pc+4, pc ← pc+imm j
jalr       rd, imm(rs1) I Jump And Link Register rd ← pc+4, pc ← (rs1+imm i)&~1
lb       rd, imm(rs1) I Load Byte rd ← sx(m8(rs1+imm i)), pc ← pc+4
lbu     rd, imm(rs1) I Load Byte Unsigned rd ← zx(m8(rs1+imm i)), pc ← pc+4
lh     rd, imm(rs1) I Load Halfword rd ← sx(m16(rs1+imm i)), pc ← pc+4
lhu     rd, imm(rs1) I Load Halfword Unsigned rd ← zx(m16(rs1+imm i)), pc ← pc+4
lui       rd, imm U Load Upper Immediate rd ← imm u, pc ← pc+4
lw     rd, imm(rs1) I Load Word rd ← sx(m32(rs1+imm i)), pc ← pc+4
or     rd, rs1, rs2 R OR rd ← rs1 | rs2, pc ← pc+4
ori     rd, rs1, imm I OR Immediate rd ← rs1 | imm i, pc ← pc+4
sb     rs2, imm(rs1) S Store Byte m8(rs1+imm s) ← rs2[7:0], pc ← pc+4
sh     rs2, imm(rs1) S Store Halfword m16(rs1+imm s) ← rs2[15:0], pc ← pc+4
sll     rd, rs1, rs2 R Shift Left Logical rd ← rs1 << (rs2%XLEN), pc ← pc+4
slli     rd, rs1, shamt I Shift Left Logical Immediate rd ← rs1 << shamt i, pc ← pc+4
slt       rd, rs1, rs2 R Set Less Than rd ← (rs1 < rs2) ? 1 : 0, pc ← pc+4
slti     rd, rs1, imm I Set Less Than Intermediate rd ← (rs1 < imm i) ? 1 : 0, pc ← pc+4
sltiu     rd, rs1, imm I Set Less Than Intermediate Unsigned rd ← (rs1 < imm i) ? 1 : 0, pc ← pc+4
sltu     rd, rs1, rs2 R Set less Than Unsigned rd ← (rs1 < rs2) ? 1 : 0, pc ← pc+4
sra       rd, rs1, rs2 R Shift Right Arithmetic rd ← rs1 >> (rs2%XLEN), pc ← pc+4
srai     rd, rs1, shamt I Shift Right Arithmetic Immediate rd ← rs1 >> shamt i, pc ← pc+4
srl       rd, rs1, rs2 R Shift Right Logical rd ← rs1 >> (rs2%XLEN), pc ← pc+4
srli      rd, rs1, shamt I Shift Right Logical Immediate rd ← rs1 >> shamt i, pc ← pc+4
sub       rd, rs1, rs2 R Subtract rd ← rs1 - rs2, pc ← pc+4
sw     rs2, imm(rs1) S Store Word m32(rs1+imm s) ← rs2[31:0], pc ← pc+4
xor       rd, rs1, rs2 R Exclusive OR rd ← rs1 ^ rs2, pc ← pc+4
xori     rd, rs1, imm I Exclusive OR Immediate rd ← rs1 ^ imm i, pc ← pc+4

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32-bit single core based implementation of RISC-V ISS feature specifications and covers all permitted configurations.

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