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Blake2s_core clock gated design fails in validation #1

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kanndil opened this issue Apr 12, 2022 · 1 comment

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kanndil commented Apr 12, 2022

The blake2s_core design passes validation as RTL, and normal gate level netlist, however fails validation after clock gating.

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kanndil commented Apr 17, 2022

Fails due to SDFFE mapping, check issue (#2).

kanndil closed this as completed

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