SDFFE mapping crashes validation

[kanndil]

The SDFFE RTLIL cell is mapped to a clock gate cell + SDFF cell. Performing clock gating on this type of cells breaks the following test cases in validation:

• blake2s
• blake2s_core
• chacha
  The validation of all test cases pass when this mapping is removed.
  Thus, this mapping is removed temporarily. Power reports will show wrong results until this issue is fixed, because the power calculations presume that all flip-flops are clock-gated.

[kanndil]

Removed SDFFE mapping from the mapfile until issue is solved

[kanndil]

Updated power reporting, considering the unmapped modules. Look at the updated benchmarks (here)