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[riscv][t1x] fix pull request mentions
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@gigiblender
gigiblender committed Dec 4, 2018
1 parent ff229a1 commit f9b1b8a
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Showing 6 changed files with 50 additions and 46 deletions.
2 changes: 1 addition & 1 deletion Jenkinsfile
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Expand Up @@ -71,7 +71,7 @@ pipeline {
dir(env.MAXINE_HOME) {
sh '$MX --J @"-Dmax.platform=linux-aarch64 -Dtest.crossisa.qemu=1 -ea" testme -s=t -junit-test-timeout=1800 -tests=junit:aarch64.asm+Aarch64T1XTest+Aarch64T1XpTest+Aarch64JTT'
sh '$MX --J @"-Dmax.platform=linux-arm -Dtest.crossisa.qemu=1 -ea" testme -s=t -junit-test-timeout=1800 -tests=junit:armv7.asm+ARMV7T1XTest+ARMV7JTT'
sh '$MX --J @"-Dmax.platform=linux-riscv64 -Dtest.crossisa.qemu=1 -ea" testme -s=t -tests=junit:riscv64.asm+max.asm.target.riscv'
sh '$MX --J @"-Dmax.platform=linux-riscv64 -Dtest.crossisa.qemu=1 -ea" testme -s=t -tests=junit:riscv64.asm+max.asm.target.riscv+riscv64.t1x'
}
}
}
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2 changes: 1 addition & 1 deletion com.oracle.max.asm/src/com/oracle/max/asm/target/riscv64/RISCV64.java
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Expand Up @@ -137,7 +137,7 @@ public class RISCV64 extends CiArchitecture {

public static final CiRegister fp = x8;

public static final CiRegister ra0 = x10;
public static final CiRegister a0 = x10;
public static final CiRegister a1 = x11;
public static final CiRegister a2 = x12;
public static final CiRegister a3 = x13;
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24 changes: 13 additions & 11 deletions com.oracle.max.asm/src/com/oracle/max/asm/target/riscv64/RISCV64MacroAssembler.java
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Expand Up @@ -26,7 +26,7 @@
import com.sun.cri.ri.RiRegisterConfig;

public class RISCV64MacroAssembler extends RISCV64Assembler {
public static final int PLACEHOLDER_INSTRUCTIONS_FOR_LONG_OFFSETS = 20;
public static final int PLACEHOLDER_INSTRUCTIONS_FOR_LONG_OFFSETS = 15;
public static final int INSTRUCTION_SIZE = 4;

public RISCV64MacroAssembler(CiTarget target) {
Expand All @@ -38,8 +38,8 @@ public RISCV64MacroAssembler(CiTarget target, RiRegisterConfig registerConfig) {
}


public final void alignForPatchableDirectCall() {
//TODO: Can we get alignment issues?
public final void alignForPatchableDirectCall(int callPos) {
assert callPos % INSTRUCTION_SIZE == 0 : "Should be 4 bytes aligned";
}

public void mov(CiRegister dst, CiRegister src) {
Expand Down Expand Up @@ -101,19 +101,21 @@ public void subi(CiRegister rd, CiRegister rs, int imm32) {
}

public void push(int size, CiRegister reg) {
assert size == 32 || size == 64 : "Unimplemented push for size: " + size;
subi(RISCV64.sp, RISCV64.sp, 16);
switch (size) {
case 64: sd(RISCV64.sp, reg, 0); break;
case 32: sw(RISCV64.sp, reg, 0); break;
default: throw new UnsupportedOperationException("Unimplemented push for size: " + size);
if (size == 64) {
sd(RISCV64.sp, reg, 0);
} else {
sw(RISCV64.sp, reg, 0);
}
}

public void pop(int size, CiRegister reg) {
switch (size) {
case 64: ld(reg, RISCV64.sp, 0); break;
case 32: lw(reg, RISCV64.sp, 0); break;
default: throw new UnsupportedOperationException("Unimplemented pop for size: " + size);
assert size == 32 || size == 64 : "Unimplemented pop for size: " + size;
if (size == 64) {
ld(reg, RISCV64.sp, 0);
} else {
lw(reg, RISCV64.sp, 0);
}
addi(RISCV64.sp, RISCV64.sp, 16);
}
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2 changes: 1 addition & 1 deletion com.oracle.max.vm.ext.t1x/src/com/oracle/max/vm/ext/t1x/riscv64/RISCV64T1XCompilation.java
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Expand Up @@ -349,7 +349,7 @@ protected void nullCheck(CiRegister src) {
}

private void alignDirectCall(int callPos) {
asm.alignForPatchableDirectCall();
asm.alignForPatchableDirectCall(callPos);
}

/**
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62 changes: 32 additions & 30 deletions com.oracle.max.vm.tests/src/com/oracle/max/vm/tests/crossisa/riscv64/t1x/RISCV64T1XTest.java
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Expand Up @@ -19,41 +19,43 @@
*/
package com.oracle.max.vm.tests.crossisa.riscv64.t1x;

import static com.sun.max.vm.MaxineVM.*;

import java.io.*;
import java.util.*;

import com.oracle.max.asm.target.riscv64.*;
import com.oracle.max.vm.ext.c1x.*;
import com.oracle.max.vm.ext.t1x.*;
import com.oracle.max.vm.ext.t1x.riscv64.*;
import com.oracle.max.asm.target.riscv64.RISCV64;
import com.oracle.max.asm.target.riscv64.RISCV64MacroAssembler;
import com.oracle.max.vm.ext.c1x.C1X;
import com.oracle.max.vm.ext.t1x.T1X;
import com.oracle.max.vm.ext.t1x.riscv64.RISCV64T1XCompilation;
import com.oracle.max.vm.tests.crossisa.riscv64.asm.MaxineRISCV64Tester;
import com.oracle.max.vm.tests.crossisa.riscv64.asm.RISCV64CodeWriter;
import com.sun.cri.bytecode.*;
import com.sun.cri.ci.*;
import com.sun.max.ide.*;
import com.sun.max.io.*;
import com.sun.max.program.option.*;
import com.sun.max.vm.actor.*;
import com.sun.max.vm.actor.member.*;
import com.sun.max.vm.classfile.*;
import com.sun.max.vm.compiler.*;
import com.sun.max.vm.hosted.*;
import com.sun.max.vm.type.*;
import com.sun.org.apache.bcel.internal.generic.FLOAD;
import com.sun.cri.bytecode.Bytecodes;
import com.sun.cri.ci.CiRegister;
import com.sun.max.ide.MaxTestCase;
import com.sun.max.program.option.OptionSet;
import com.sun.max.vm.actor.Actor;
import com.sun.max.vm.actor.member.StaticMethodActor;
import com.sun.max.vm.classfile.CodeAttribute;
import com.sun.max.vm.classfile.LineNumberTable;
import com.sun.max.vm.classfile.LocalVariableTable;
import com.sun.max.vm.compiler.CompilationBroker;
import com.sun.max.vm.compiler.RuntimeCompiler;
import com.sun.max.vm.hosted.JavaPrototype;
import com.sun.max.vm.hosted.VMConfigurator;
import com.sun.max.vm.type.Kind;
import com.sun.max.vm.type.SignatureDescriptor;

import java.util.ArrayList;
import java.util.LinkedList;
import java.util.List;

import static com.sun.max.vm.MaxineVM.Phase;
import static com.sun.max.vm.MaxineVM.vm;

public class RISCV64T1XTest extends MaxTestCase {

// private RISCV64Assembler asm;
// private CiTarget riscv64;
// private RISCV64CodeWriter code;
private T1X t1x;
private C1X c1x;
private T1X t1x;
private C1X c1x;
private RISCV64T1XCompilation theCompiler;
private StaticMethodActor anMethod = null;
private CodeAttribute codeAttr = null;
// private static boolean POST_CLEAN_FILES = true;

public void initialiseFrameForCompilation() {
// TODO: compute max stack
Expand Down Expand Up @@ -93,10 +95,12 @@ static final class Pair {
private static VMConfigurator vmConfigurator = null;
private static boolean initialised = false;

private static MaxineRISCV64Tester.BitsFlag[] bitmasks = new MaxineRISCV64Tester.BitsFlag[MaxineRISCV64Tester.NUM_REGS];
private static MaxineRISCV64Tester.BitsFlag[] bitmasks = new MaxineRISCV64Tester.BitsFlag[MaxineRISCV64Tester.NUM_REGS];

static {
MaxineRISCV64Tester.setAllBitMasks(bitmasks, MaxineRISCV64Tester.BitsFlag.All64Bits);
}

private static boolean[] testValues = new boolean[MaxineRISCV64Tester.NUM_REGS];

private static void resetIgnoreValues() {
Expand All @@ -109,8 +113,6 @@ private static void resetIgnoreValues() {
// to those expected to be found in a register after simulated execution of code.
private static long[] expectedValues = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};

// private static long[] expectedLongValues = {Long.MAX_VALUE - 100, Long.MAX_VALUE};
//
private static void initialiseExpectedValues() {
for (int i = 0; i < MaxineRISCV64Tester.NUM_REGS; i++) {
expectedValues[i] = i;
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4 changes: 2 additions & 2 deletions com.sun.max/src/com/sun/max/vm/compiler/target/RegisterConfigs.java
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Expand Up @@ -431,7 +431,7 @@ public static RegisterConfigs create() {
*/
standard = new CiRegisterConfig(
RISCV64.fp, // frame
RISCV64.ra0, // integral return value
RISCV64.a0, // integral return value
RISCV64.fa0, // floating point return value
RISCV64.x28, // scratch
RISCV64.x29, // scratch 1
Expand Down Expand Up @@ -472,7 +472,7 @@ public static RegisterConfigs create() {
roleMap.put(ABI_FP, RISCV64.fp);
CiRegisterConfig template = new CiRegisterConfig(
RISCV64.fp, // frame???
RISCV64.ra0, // integral return value
RISCV64.a0, // integral return value
RISCV64.fa0, // floating point return value
RISCV64.x28, // scratch
RISCV64.x29, // scratch 1
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