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Arm v8.2 #8

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237e359
A32: Arm and Thumb v8.1 instructions
jkressel Jul 27, 2022
cb539b0
A32: v8.2 instruction encodings
jkressel Aug 9, 2022
cfa979b
A64: ARM v8.2
jkressel Aug 4, 2022
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24 changes: 21 additions & 3 deletions a64.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -84,20 +84,24 @@ logical_reg abb01010 ccdeeeee ffffffgg ggghhhhh, a:sf, b:opc, c:shif
simd_across_lane 0ab01110 cc11000d dddd10ee eeefffff, a:q, b:u, c:size, d:opcode, e:rn, f:rd
simd_copy 0ab01110 000ccccc 0dddd1ee eeefffff, a:q, b:op, c:imm5, d:imm4, e:rn, f:rd
simd_extract 0a101110 000bbbbb 0cccc0dd dddeeeee, a:q, b:rm, c:imm4, d:rn, e:rd
simd_modified_immed 0ab01111 00000ccc dddd01ee eeefffff, a:q, b:op, c:abc, d:cmode, e:defgh, f:rd
simd_modified_immed 0ab01111 00000ccc ddddo1ee eeefffff, a:q, b:op, c:abc, d:cmode, o:o2, e:defgh, f:rd
simd_permute 0a001110 bb0ccccc 0ddd10ee eeefffff, a:q, b:size, c:rm, d:opcode, e:rn, f:rd
simd_scalar_copy 01011110 000aaaaa 000001bb bbbccccc, a:imm5, b:rn, c:rd
simd_scalar_pairwise 01a11110 bb11000c cccc10dd dddeeeee, a:u, b:size, c:opcode, d:rn, e:rd
simd_scalar_shift_immed 01a11111 0bbbbccc ddddd1ee eeefffff, a:u, b:immh, c:immb, d:opcode, e:rn, f:rd
simd_scalar_three_diff 01a11110 bb1ccccc dddd00ee eeefffff, a:u, b:size, c:rm, d:opcode, e:rn, f:rd
simd_scalar_three_same 01a11110 bb1ccccc ddddd1ee eeefffff, a:u, b:size, c:rm, d:opcode, e:rn, f:rd
simd_scalar_three_same_fp16 01a11110 b10ccccc 00ddd1ee eeefffff, a:u, b:a, c:rm, d:opcode, e:rn, f:rd
simd_scalar_two_reg 01a11110 bb10000c cccc10dd dddeeeee, a:u, b:size, c:opcode, d:rn, e:rd
simd_scalar_two_reg_fp16 01a11110 b111100c cccc10dd dddeeeee, a:u, b:a, c:opcode, d:rn, e:rd
simd_scalar_x_indexed 01a11111 bbcdeeee ffffg0hh hhhiiiii, a:u, b:size, c:l, d:m, e:rm, f:opcode, g:H, h:rn, i:rd
simd_shift_immed 0ab01111 0ccccddd eeeee1ff fffggggg, a:q, b:u, c:immh:!:0000, d:immb, e:opcode, f:rn, g:rd
simd_table_lookup 0a001110 000bbbbb 0ccd00ee eeefffff, a:q, b:rm, c:len, d:op, e:rn, f:rd
simd_three_diff 0ab01110 cc1ddddd eeee00ff fffggggg, a:q, b:u, c:size, d:rm, e:opcode, f:rn, g:rd
simd_three_same 0ab01110 cc1ddddd ccccc1dd dddeeeee, a:q, b:u, c:size, d:rm, c:opcode, d:rn, e:rd
simd_three_same_fp16 0ab01110 c10ddddd 00eee1ff fffggggg, a:q, b:u, c:a, d:rm, e:opcode, f:rn, g:rd
simd_two_reg 0ab01110 cc10000d dddd10ee eeefffff, a:q, b:u, c:size, d:opcode, e:rn, f:rd
simd_two_reg_fp16 0ab01110 c111100d dddd10ee eeefffff, a:q, b:u, c:a, d:opcode, e:rn, f:rd
simd_x_indexed 0ab01111 ccdeffff ggggh0ii iiijjjjj, a:q, b:u, c:size, d:l, e:m, f:rm, g:opcode, h:H, i:rn, j:rd
crypto_aes 01001110 0010100a aaaa10bb bbbccccc, a:opcode, b:rn, c:rd
crypto_sha_reg3 01011110 000aaaaa 0ccc00dd dddeeeee, a:rm, c:opcode, d:rn, e:rd
Expand All @@ -109,5 +113,19 @@ float_reg1 00011110 aa1bbbbb b10000cc cccddddd, a:type, b:opcode, c
float_reg2 00011110 aa1bbbbb cccc10dd dddeeeee, a:type, b:rm, c:opcode, d:rn, e:rd
float_reg3 00011111 aabccccc deeeeeff fffggggg, a:type, b:o1, c:rm, d:o0, e:Ra, f:rn, g:rd
FMOV_immed 00011110 aa1bbbbb bbb10000 000ccccc, a:type, b:imm8, c:rd
float_cvt_fixed a0011110 bb0ccddd eeeeeeff fffggggg, a:sf, b:type, c:rmode, d:opcode, e:scale, f:rn, g:rd
float_cvt_int a0011110 bb1ccddd 000000ee eeefffff, a:sf, b:type, c:rmode, d:opcode, e:rn, f:rd
float_immed a0b11110 cc1ddddd ddd100ee eeefffff, a:m, b:s, c:ptype, d:imm8, e:imm5, f:rd
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@lgeek lgeek Jan 10, 2023 •
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As far as I can see on page C4-321, all the allocated instructions covered by float_immed are already covered by FMOV_immed so I don't think float_immed is needed. Please double check this. In any case, we should only keep one of these 2 definitions.

float_cvt_fixed a0s11110 bb0ccddd eeeeeeff fffggggg, a:sf, s:s, b:type, c:rmode, d:opcode, e:scale, f:rn, g:rd
float_cvt_int a0s11110 bb1ccddd 000000ee eeefffff, a:sf, s:s, b:type, c:rmode, d:opcode, e:rn, f:rd
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Same as above for float_cvt_fixed and float_cvt_int, it doesn't look like S(bit 29)=1 for any of the instructions defined in ARMv8.2 (page C4-311).

simd_three_reg_ext 0ab01110 cc0ddddd 1oooo1ee eeefffff, a:q, b:u, c:size, d:rm, e:rn, f:rd, o:opcode
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This is 'Advanced SIMD three same extra (page C4-296)', right? The name should be updated to better match the documentation

sve_float_mat_mult_acc 01100100 aa1bbbbb 111001cc cccddddd, a:opc, b:zm, c:zn, d:zda
sve_ld_bcast_quad_scal_immed 1010010a abb0cccc 001dddee eeefffff, a:msz, b:ssz, c:imm4, d:pg, e:rn, f:zt
sve_ld_bcast_quad_scal_scal 1010010a abbccccc 000dddee eeefffff, a:msz, b:ssz, c:rm, d:pg, e:rn, f:zt
sve_permute_vector 00000101 101aaaaa 000bbcdd dddeeeee, a:zm, b:opc, c:h, d:zn, e:zd
sve_permute_vector_el 00000101 aa1bbbbb 011cccdd dddeeeee, a:size, b:zm, c:opc, d:zn, e:zd
sve_permute_vector_pred_el 00000101 aa10bbbb 010ccd0e eee0ffff, a:size, b:pm, c:opc, d:h, e:pn, f:pd
sve_permute_vector_seg 00000101 101aaaaa 000bbcdd dddeeeee, a:zm, b:opc, c:h, d:zn, e:zd
crypto_sha512_reg3 11001110 011aaaaa 1b00ccdd dddeeeee, a:rm, b:o, c:opcode, d:rn, e:rd
crypto_sha512_reg2 11001110 11000000 1000aabb bbbccccc, a:opcode, b:rn, c:rd
crypto_reg4 11001110 0aabbbbb 0cccccdd dddeeeee, a:op0, b:rm, c:ra, d:rn, e:rd
crypto_reg3_imm2 11001110 010aaaaa 10bbccdd dddeeeee, a:rm, b:imm2, c:opcode, d:rn, e:rd
sve_xar 00000100 aa1bbccc 001101dd dddeeeee, a:tszh, b:tszl, c:imm3, d:zm, e:zdn
19 changes: 19 additions & 0 deletions arm.txt
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Expand Up @@ -105,6 +105,7 @@ sbfx aaaa0111 101bbbbb ccccdddd d101eeee, a:auto_cond, c:rd, e:rn, d
sdiv aaaa0111 0001bbbb 1111cccc 0001dddd, a:auto_cond, b:rd, d:rn, c:rm
sel aaaa0110 1000bbbb cccc1111 1011dddd, a:auto_cond, c:rd, b:rn, d:rm
setend 11110001 00000001 000000e0 00000000, e:set_bigend
setpan 11110001 00010000 000000a0 00000000, a:imm
sev aaaa0011 00100000 11110000 00000100, a:auto_cond
shadd16 aaaa0110 0011bbbb cccc1111 0001dddd, a:auto_cond, c:rd, b:rn, d:rm
shadd8 aaaa0110 0011bbbb cccc1111 1001dddd, a:auto_cond, c:rd, b:rn, d:rm
Expand Down Expand Up @@ -285,7 +286,10 @@ neon_vdup_scal 11110011 1d11aaaa bbbb1100 0qm0cccc, a:auto_cond, q:q, a:im
neon_vdup_core aaaa1110 1bq0cccc ffff1011 d0e10000, a:auto_cond, b:b, e:e, q:q, d:d, c:vd, f:rt
neon_veor 11110011 0d00aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vext 11110010 1d11aaaa bbbbcccc nqm0eeee, q:q, d:d, b:vd, n:n, a:vn, m:m, e:vm, c:imm4
vfp_vins_hp 11111110 1a110000 bbbb1010 11c0dddd, a:d, b:vd, c:m, d:vm
neon_vfma 11110010 0d0saaaa bbbb1100 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
vfp_vfmal_el 11111110 0a00bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
vfp_vfmal_vec 11111100 0a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vfms 11110010 0d1saaaa bbbb1100 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
vfp_vfma aaaa1110 1d10bbbb cccc101s n0m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm
vfp_vfms aaaa1110 1d10bbbb cccc101s n1m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm
Expand Down Expand Up @@ -325,9 +329,13 @@ neon_vmovi 1111001i 1d000aaa bbbbcccc 0qo1eeee, q:q, d:d, b:vd, o:op,
vfp_vmov_core_sp aaaa1110 000obbbb cccc1010 n0010000, a:auto_cond, o:op, c:rt, n:n, b:vn
vfp_vmov_2core_2sp aaaa1100 010obbbb cccc1010 00m1dddd, a:auto_cond, o:op, c:rt, b:rt2, m:m, d:vm
vfp_vmov_2core_dp aaaa1100 010obbbb cccc1011 00m1dddd, a:auto_cond, o:op, c:rt, b:rt2, m:m, d:vm
vfp_vmov_hp aaaa1110 000bcccc dddd1001 e0010000, a:cond, b:op, d:rt, e:n, c:vn
vfp_vmovx_hp 11111110 1a110000 bbbb1010 01c0dddd, a:d, b:vd, c:m, d:vm
neon_vmovl 1111001u 1daaa000 bbbb1010 00m1cccc, u:unsign, d:d, b:vd, m:m, c:vm, a:imm3
neon_vmovn 11110011 1d11ss10 aaaa0010 00m0bbbb, s:size, d:d, a:vd, m:m, b:vm
vfp_vmrs aaaa1110 11110001 bbbb1010 00010000, a:auto_cond, b:rt
vfp_vfmsl_el 11111110 0a01bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
vfp_vfmsl_vec 11111100 1a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
vfp_vmsr aaaa1110 11100001 bbbb1010 00010000, a:auto_cond, b:rt
neon_vmul_i 1111001a 0bccdddd eeee1001 fgh1iiii, a:opcode, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm
neon_vmull_i 1111001a 1bccdddd eeee11f0 g0h0iiii, a:opcode, f:opcode4, c:size, b:d, e:vd, g:n, d:vn, h:m, i:vm
Expand Down Expand Up @@ -370,6 +378,10 @@ neon_vqdmull_scal 11110010 1dssaaaa bbbb1011 n1m0cccc, s:size, d:d, b:vd, n:n
neon_vqmovn 11110011 1d11ss10 aaaa0010 1om0bbbb, o:unsign, s:size, d:d, a:vd, m:m, b:vm
neon_vqmovun 11110011 1d11ss10 aaaa0010 01m0bbbb, s:size, d:d, a:vd, m:m, b:vm
neon_vqneg 11110011 1d11ss00 aaaa0111 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm
neon_vqrdmlaha1 11110011 0abbcccc dddd1011 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm
neon_vqrdmlaha2 1111001a 1bccdddd eeee1110 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm
neon_vqrdmlsha1 11110011 0abbcccc dddd1100 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm
neon_vqrdmlsha2 1111001a 1bccdddd eeee1111 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm
neon_vqrdmulh_i 11110011 0dssaaaa bbbb1011 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vqrdmulh_scal 1111001q 1dssaaaa bbbb1101 n1m0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vqrshl 1111001u 0dssaaaa bbbb0101 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
Expand All @@ -395,6 +407,9 @@ neon_vrsqrte 11110011 1d11ss11 aaaa010f 1qm0bbbb, f:floating_point, s:si
neon_vrsqrts 11110010 0d1saaaa bbbb1111 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vrsra 1111001u 1daaaaaa bbbb0011 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6
neon_vrsubhn 11110011 1dssaaaa bbbb0110 n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vsdot_el 11111110 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm
neon_vsdot_vec 11111100 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm
neon_vsudot_el 11111110 1a00bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vshl 1111001u 0dssaaaa bbbb0100 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vshli 11110010 1daaaaaa bbbb0101 lqm1cccc, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6
neon_vshll 1111001u 1daaaaaa bbbb1010 00m1cccc, u:unsign, d:d, b:vd, m:m, c:vm, a:imm6
Expand Down Expand Up @@ -422,6 +437,10 @@ neon_vtbl 11110011 1d11aaaa bbbb10cc n0m0eeee, d:d, b:vd, n:n, a:vn,
neon_vtbx 11110011 1d11aaaa bbbb10cc n1m0eeee, d:d, b:vd, n:n, a:vn, c:len, m:m, e:vm
neon_vtrn 11110011 1a11bb10 cccc0000 1de0ffff, b:size, d:q, a:d, c:vd, e:m, f:vm
neon_vtst 11110010 0dssaaaa bbbb1000 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vudot_el 11111110 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vudot_vec 11111100 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vusdot_el 11111110 1a00bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vusdot_vec 11111100 1a10bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vuzp 11110011 1d11ss10 aaaa0001 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm
neon_vzip 11110011 1d11ss10 aaaa0001 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm

Expand Down
19 changes: 19 additions & 0 deletions thumb.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -82,6 +82,7 @@ ror16 01000001 11aaabbb, a:rm, b:rdn
rsbi16 01000010 01aaabbb, a:rm, b:rdn
sbc16 01000001 10aaabbb, a:rm, b:rdn
setend16 10110110 0101e000, e:is_bigend
setpan 10110110 0001a000, a:imm
sev16 10111111 01000000
stmea16 11000aaa bbbbbbbb, a:rn, b:reglist
str16 0101000a aabbbccc, a:rm, b:rn, c:rd
Expand Down Expand Up @@ -429,10 +430,15 @@ neon_vdup_scal 11111111 1a11bbbb cccc1100 0de0ffff, d:q, b:imm4, a:d, c:vd,
neon_vdup_core 11101110 1bq0aaaa cccc1011 d0e10000, b:b, e:e, q:q, d:d, a:vd, c:rt
neon_veor 11111111 0a00bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vext 11101111 1a11bbbb ccccdddd efg0hhhh, f:q, a:d, c:vd, e:n, b:vn, g:m, h:vm, d:imm4
vfp_vins_hp 11111110 1a110000 bbbb1010 11c0dddd, a:d, b:vd, c:m, d:vm
neon_vfma 11101111 0a0sbbbb cccc1100 nqm1dddd, s:size, q:q, a:d, c:vd, n:n, b:vn, m:m, d:vm
neon_vfms 11101111 0a1sbbbb cccc1100 nqm1dddd, s:size, q:q, a:d, c:vd, n:n, b:vn, m:m, d:vm
vfp_vfma 11101110 1d10aaaa bbbb101s n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm
vfp_vfmal_el 11111110 0a00bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
vfp_vfmal_vec 11111100 0a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
vfp_vfms 11101110 1d10aaaa bbbb101s n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm
vfp_vfmsl_el 11111110 0a01bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
vfp_vfmsl_vec 11111100 1a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
vfp_vfnma 11101110 1d01aaaa bbbb101s n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm
vfp_vfnms 11101110 1d01aaaa bbbb101s n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vhadd 111a1111 0bccdddd eeee0000 fgh0iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm
Expand Down Expand Up @@ -468,6 +474,8 @@ neon_vmovi 111a1111 1b000ccc ddddeeee 0fg1hhhh, f:q, b:d, d:vd, g:op, e
vfp_vmov_core_sp 11101110 000oaaaa bbbb1010 n0010000, o:op, b:rt, n:n, a:vn
vfp_vmov_2core_2sp 11101100 010abbbb cccc1010 00d1eeee, a:to_arm, c:rt, b:rt2, d:m, e:vm
vfp_vmov_2core_dp 11101100 010abbbb cccc1011 00d1eeee, a:to_arm, c:rt, b:rt2, d:m, e:vm
vfp_vmov_hp 11101110 000abbbb cccc1001 d0010000, a:op, c:rt, d:n, b:vn
vfp_vmovx_hp 11111110 1a110000 bbbb1010 01c0dddd, a:d, b:vd, c:m, d:vm
neon_vmovl 111u1111 1daaa000 bbbb1010 00m1cccc, a:op:!:000, u:unsign, d:d, b:vd, m:m, c:vm
neon_vmovn 11111111 1d11ss10 aaaa0010 00m0bbbb, s:size, d:d, a:vd, m:m, b:vm
vfp_vmrs 11101110 11110001 aaaa1010 00010000, a:rt
Expand Down Expand Up @@ -511,6 +519,10 @@ neon_vqdmull_scal 11101111 1dssaaaa bbbb1011 n1m0cccc, s:size:!:11, d:d, b:vd,
neon_vqmovn 11111111 1a11bb10 cccc0010 1de0ffff, d:unsign, b:size, a:d, c:vd, e:m, f:vm
neon_vqmovun 11111111 1a11bb10 cccc0010 01d0ffff, b:size, a:d, c:vd, d:m, f:vm
neon_vqneg 11111111 1d11ss00 aaaa0111 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm
neon_vqrdmlaht1 11111111 0abbcccc dddd1011 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm
neon_vqrdmlaht2 111a1111 1bccdddd eeee1110 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm
neon_vqrdmlsht1 11111111 0abbcccc dddd1100 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm
neon_vqrdmlsht2 111a1111 1bccdddd eeee1111 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm
neon_vqrdmulh_i 11111111 0dssaaaa bbbb1011 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vqrdmulh_scal 111q1111 1dssaaaa bbbb1101 n1m0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vqrshl 111u1111 0dssaaaa bbbb0101 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
Expand All @@ -536,6 +548,8 @@ neon_vrsqrte 11111111 1d11ss11 aaaa010f 1qm0bbbb, f:is_float, s:size, q:q
neon_vrsqrts 11101111 0d1saaaa bbbb1111 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vrsra 111u1111 1daaaaaa bbbb0011 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6
neon_vrsubhn 11111111 1dssaaaa bbbb0110 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vsdot_el 11111110 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm
neon_vsdot_vec 11111100 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm
neon_vshl 111a1111 0bccdddd eeee0100 fgh0iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm
neon_vshli 11101111 1abbbbbb cccc0101 def1gggg, e:q, a:d, c:vd, f:m, g:vm, d:l, b:imm6
neon_vshll 111a1111 1bcccccc dddd1010 00e1ffff, a:unsign, b:d, d:vd, e:m, f:vm, c:imm6:!:000000:000001:000010:000011:000100:000101:000110:000111
Expand All @@ -558,11 +572,16 @@ neon_vsub_f 11101111 0d1saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd,
neon_vsubhn 11101111 1abbcccc dddd0110 e0f0gggg, b:size:!:11, a:d, d:vd, e:n, c:vn, f:m, g:vm
neon_vsubl 111a1111 1bccdddd eeee0010 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm
neon_vsubw 111a1111 1bccdddd eeee0011 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm
neon_vsudot_el 11111110 1a00bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vswp 11111111 1d11ss10 aaaa0000 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm
neon_vtbl 11111111 1d11aaaa bbbb10cc n0m0eeee, d:d, b:vd, n:n, a:vn, c:len, m:m, e:vm
neon_vtbx 11111111 1d11aaaa bbbb10cc n1m0eeee, d:d, b:vd, n:n, a:vn, c:len, m:m, e:vm
neon_vtrn 11111111 1a11bb10 cccc0000 1de0ffff, b:size, d:q, a:d, c:vd, e:m, f:vm
neon_vtst 11101111 0dssaaaa bbbb1000 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm
neon_vudot_el 11111110 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vudot_vec 11111100 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vusdot_el 11111110 1a00bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vusdot_vec 11111100 1a10bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm
neon_vuzp 11111111 1d11ss10 aaaa0001 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm
neon_vzip 11111111 1d11ss10 aaaa0001 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm
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