[trace-replay] added the general trace-replay module with examples.

bsg_test/bsg_trace_replay.v

@@ -0,0 +1,199 @@
+`include "bsg_defines.v"
+
+// MBT 11/26/2014,      bsg_fsb_node_trace_replay
+// Shaolin 01/06/2018,  generalized from the bsg_trace_replay
+// trace format (see enum below)
+//
+
+module bsg_trace_replay
+  #(  parameter payload_width_p =80
+    , parameter rom_addr_width_p=6
+    , parameter counter_width_p=`BSG_MIN(payload_width_p,16)
+     //The operation code is always 4 bits.
+    , parameter opcode_width_lp = 4
+    )
+   (  input clk_i
+    , input reset_i
+    , input en_i
+
+    // input channel
+    , input v_i
+    , input [payload_width_p-1:0] data_i
+    , output logic ready_o
+
+    // output channel
+    , output logic v_o
+    , output logic [payload_width_p-1:0] data_o
+    , input yumi_i
+
+    // connection to rom
+    // note: asynchronous reads
+
+    , output [rom_addr_width_p-1:0] rom_addr_o
+    , input  [payload_width_p+4-1:0]   rom_data_i
+
+    // true outputs
+    , output logic done_o
+    , output logic error_o
+    );
+
+   // 0: wait one cycle
+   // 1: send data
+   // 2: receive data (and check its value)
+   // 3: assert done_o; test complete.
+   // 4: end test; call $finish
+   // 5: decrement cycle counter; wait for cycle_counter == 0
+   // 6: initialized cycle counter with 16 bits
+   // in theory, we could add branching, etc.
+   // before we know it, we have a processor =)
+
+   typedef enum logic [opcode_width_lp-1:0] {
+      eNop=4'd0,
+      eSend=4'd1,
+      eReceive=4'd2,
+      eDone=4'd3,
+      eFinish=4'd4,
+      eCycleDec=4'd5,
+      eCycleInit=4'd6
+   } eOp;
+
+
+   logic [counter_width_p-1:0] cycle_ctr_r, cycle_ctr_n;
+
+   logic [rom_addr_width_p-1:0] addr_r, addr_n;
+   logic                        done_r, done_n;
+   logic                        error_r, error_n;
+
+   assign rom_addr_o = addr_r;
+   assign data_o     = rom_data_i[0+:payload_width_p];
+   assign done_o     = done_r;
+   assign error_o    = error_r;
+
+   always_ff @(posedge clk_i) begin
+   if (reset_i) begin
+             addr_r      <= 0;
+             done_r      <= 0;
+             error_r     <= 0;
+             cycle_ctr_r <= 16'b1;
+   end else begin
+             addr_r      <= addr_n;
+             done_r      <= done_n;
+             error_r     <= error_n;
+             cycle_ctr_r <= cycle_ctr_n;
+       end
+   end // always_ff @
+
+   logic [3:0] op;
+   assign op = rom_data_i[payload_width_p+:4];
+
+   logic      instr_completed;
+
+   assign addr_n =  instr_completed ? (addr_r+1'b1) : addr_r;
+
+   // handle outputs
+   always_comb begin
+        // defaults; not sending and not receiving unless done
+        v_o             = 1'b0;
+        ready_o         = done_r;
+        done_n          = done_r;
+
+        if (!done_r & en_i & ~reset_i) begin
+             case (op)
+               eSend:    v_o     = 1'b1;
+               eReceive: ready_o = 1'b1;
+               eDone:    done_n  = 1'b1;
+               default:
+                 begin
+                 end
+             endcase
+          end
+     end // always_comb
+
+   // next instruction logic
+   always_comb begin
+        instr_completed = 1'b0;
+        error_n = error_r;
+        cycle_ctr_n = cycle_ctr_r;
+
+        if (!done_r & en_i & ~reset_i) begin
+             case (op)
+               eNop:              instr_completed = 1'b1;
+               eSend: if (yumi_i) instr_completed = 1'b1;
+               eReceive: begin
+                    if (v_i)
+                      begin
+                         instr_completed = 1'b1;  
+                         if (error_r == 0)
+                            error_n = data_i != data_o;
+                      end
+                 end
+               eDone:             instr_completed = 1'b1;
+               eFinish:           instr_completed = 1'b1;
+               eCycleDec:
+                 begin
+                    cycle_ctr_n = cycle_ctr_r - 1'b1;
+                    instr_completed = ~(|cycle_ctr_r);
+                 end
+               eCycleInit:
+                 begin
+                    cycle_ctr_n = rom_data_i[counter_width_p-1:0];
+                    instr_completed = 1;
+                 end
+               default:
+                 begin
+                 end
+             endcase // case (op)
+          end
+     end
+
+   // non-synthesizeable components
+   always @(negedge clk_i) begin
+        if (instr_completed & ~reset_i & ~done_r) begin
+             case(op)
+               eSend: $display("### bsg_trace_replay SEND %d'b%b (%m)", payload_width_p,data_o);
+               eReceive: begin
+                    if (data_i !== data_o) begin
+                         $display("############################################################################");
+                         $display("### bsg_trace_replay RECEIVE unmatched (%m) ");
+                         $display("###    ");
+                         $display("### FAIL (trace mismatch) = %h", data_i);
+                         $display("###              expected = %h\n", data_o);
+                         $display("############################################################################");
+                         $finish();
+                    end else begin
+                         $display("### bsg_trace_replay RECEIVE matched %h (%m)", data_o);
+                    end // else: !if(data_i != data_o)
+               end
+               eDone: begin
+                    $display("############################################################################");
+                    $display("###### bsg_trace_replay DONE done_o=1 (trace finished addr=%x) (%m)",rom_addr_o);
+                    $display("############################################################################");
+               end
+               eFinish: begin
+                    $display("############################################################################");
+                    $display("###### bsg_trace_replay FINISH (trace finished; CALLING $finish) (%m)");
+                    $display("############################################################################");
+                    $finish;
+               end
+               eCycleDec: begin
+                    $display("### bsg_trace_replay CYCLE DEC cycle_ctr_r = %x (%m)",cycle_ctr_r);
+               end
+               eCycleInit: begin
+                    $display("### bsg_trace_replay CYCLE INIT = %x (%m)",cycle_ctr_n);
+               end
+               default:
+                 begin
+
+                 end
+             endcase // case (op)
+
+             case (op)
+               eNop, eSend, eReceive, eDone, eFinish, eCycleDec, eCycleInit:
+                 begin
+                 end
+               default: $display("### bsg_trace_replay UNKNOWN op %x (%m)\n", op);
+             endcase // case (op)
+          end // if (instr_completed & ~reset_i & ~done_r)
+     end // always @ (negedge clk_i)
+
+endmodule

testing/bsg_test/bsg_trace_replay/Makefile

@@ -0,0 +1,52 @@
+###########################################
+# DEFINE THE PATHS
+BSG_IP_CORES_DIR=$(abspath  ../../../../bsg_ip_cores)
+BSG_MANYCORE_DIR=$(abspath  ../../../../bsg_manycore)
+
+CADENV_DIR=$(abspath ../../../../bsg_cadenv)
+
+###########################################
+# SETUP THE TOOL PATHS
+include $(CADENV_DIR)/cadenv.mk
+
+#############################################
+# SETUP THE INCLUDE PATH and SEARCH PATH
+INC_DIRS	+= $(BSG_IP_CORES_DIR)/bsg_misc
+
+SRC_DIRS	+= $(BSG_IP_CORES_DIR)/bsg_misc
+SRC_DIRS	+= $(BSG_IP_CORES_DIR)/bsg_test
+SRC_DIRS	+= ./
+
+PKG_FILES	+= $(BSG_IP_CORES_DIR)/bsg_misc/bsg_defines.v
+
+###########################################
+# DEFINE THE VCS OPTIONS
+VCS_OP	    =-full64 -sverilog
+# compile and run 
+VCS_OP     += -R
+# search *.v files for module
+VCS_OP     += +libext+.v
+#enable waveform dump
+VCS_OP     +=  +vcs+vcdpluson -debug_pp
+#setup the timescale
+VCS_OP     += -timescale=1ns/1ps
+
+run: stimulus_rom.v response_rom.v
+	$(VCS) $(VCS_OP) 			\
+	$(addprefix +incdir+, $(INC_DIRS) )	\
+	$(addprefix -y , $(SRC_DIRS)     )	\
+	$(PKG_FILES)				\
+	test_bench.v -top test_bench
+
+stimulus_rom.v:
+	$(BSG_IP_CORES_DIR)/bsg_mem/bsg_ascii_to_rom.py stimulus.trace.in stimulus_rom > $@
+
+response_rom.v:
+	$(BSG_IP_CORES_DIR)/bsg_mem/bsg_ascii_to_rom.py response.trace.out response_rom > $@
+
+dve:
+	$(VCS_BIN)/dve -full64 -vpd vcdplus.vpd &
+
+clean:
+	rm -rf csrc DVEfiles *.tar.gz simv simv.daidir ucli.key vcdplus.vpd *_rom.v
+

testing/bsg_test/bsg_trace_replay/dut.v

@@ -0,0 +1,21 @@
+module dut
+  #(  parameter payload_width_p =80
+   ) (  input clk_i
+      , input reset_i
+
+    // input channel
+    , input v_i
+    , input [payload_width_p-1:0] data_i
+    , output logic ready_o
+
+    // output channel
+    , output logic v_o
+    , output logic [payload_width_p-1:0] data_o
+    , input ready_i
+    );
+
+assign v_o     = v_i            ;
+assign ready_o = ready_i        ;
+assign data_o  = ~data_i        ;
+
+endmodule

testing/bsg_test/bsg_trace_replay/response.trace.out

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+# cmd[3:0] + 32 bits paylod 
+# cmd formats refer to bsg_ip_cores/bsg_test/bsg_trace_replay.v comments.
+# In this example, the response is supposed to be the reversed stimulus.
+
+# record 0, recieve data 
+0010____1111_1111_1111_1111_____1111_1111_1111_1110
+# record 1, recieve data 
+0010____1111_1111_1111_1111_____1111_1111_1111_1101
+# record 2, recieve data
+0010____1111_1111_1111_1111_____1111_1111_1111_1100
+# record 3, done, pull up done_o signal
+0011____0000_0000_0000_0000_____0000_0000_0000_0000
+
+

testing/bsg_test/bsg_trace_replay/stimulus.trace.in

@@ -0,0 +1,15 @@
+# cmd[3:0] + 32 bits paylod 
+# cmd formats refer to bsg_ip_cores/bsg_test/bsg_trace_replay.v comments.
+#
+
+# record 0, send out data 
+0001____0000_0000_0000_0000_____0000_0000_0000_0001
+# record 1, send out data 
+0001____0000_0000_0000_0000_____0000_0000_0000_0010
+# record 2, NOP (wait 1 cycle)
+0000____0000_0000_0000_0000_____0000_0000_0000_0000
+# record 3, send out data
+0001____0000_0000_0000_0000_____0000_0000_0000_0011
+# record 4, done
+0011____0000_0000_0000_0000_____0000_0000_0000_0000
+