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If CS is asserted between transfers then consider bus to be busy for all but owning device #12604

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merged 3 commits into from May 10, 2023
Merged

If CS is asserted between transfers then consider bus to be busy for all but owning device #12604

merged 3 commits into from May 10, 2023

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SteveCEvans
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May fix #12583.

This PR checks if CS is asserted between transfers and then consider the SPI bus to be busy for all but the device which asserted CS.

@SteveCEvans SteveCEvans changed the title If CS is asserted between transfers then consider bus to be busy for … If CS is asserted between transfers then consider bus to be busy for all but owning device Mar 31, 2023
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@SteveCEvans SteveCEvans self-assigned this Mar 31, 2023
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@blckmn
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blckmn commented Mar 31, 2023 •
edited

AUTOMERGE: (FAIL)

  • github identifies PR as mergeable -> FAIL
  • assigned to a milestone -> PASS
  • cooling off period lapsed -> PASS
  • commit count less or equal to three -> PASS
  • Don't merge label NOT found -> PASS
  • at least one RN: label found -> PASS
  • Tested label found -> FAIL
  • assigned to an approver -> PASS
  • approver count at least three -> FAIL

@cwei cwei mentioned this pull request Mar 31, 2023
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freasy
freasy approved these changes Apr 27, 2023
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@freasy freasy left a comment •
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tested on MAMBAG4 which has a shared SPI bus for flash and OSD

before: OSD locks up and blackbox stops working
after: OSD works perfect, blackbox logs as expected

edit://
its not fixed, i dont know why it worked once here

edit2://
DMA resource mapping must be done manual, if BUS is shared! So i can declare this as tested on 2 G4 boards.

haslinghuis
haslinghuis approved these changes Apr 27, 2023
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@haslinghuis haslinghuis left a comment •
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@SteveCEvans is this ready to merge?

EDIT - SPI DMA: If bus is shared we need to assign manual:

#define SPI_RX_DMA_OPT 6
#define SPI_TX_DMA_OPT 7
#define SPI_RX_DMA_OPT 8
#define SPI_TX_DMA_OPT 9

@SteveCEvans
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I need to fix an issue with the MAMBAG4 build to complete testing.

@SteveCEvans
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@SteveCEvans is this ready to merge?

EDIT - SPI DMA: If bus is shared we need to assign manual:

#define SPI_RX_DMA_OPT 6
#define SPI_TX_DMA_OPT 7
#define SPI_RX_DMA_OPT 8
#define SPI_TX_DMA_OPT 9

These definitions are meaningless.

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@SteveCEvans I got those lines from @freasy .
Should be

#define SPI1_RX_DMA_OPT 6
#define SPI1_TX_DMA_OPT 7
#define SPI2_RX_DMA_OPT 8
#define SPI2_TX_DMA_OPT 9

Updated in config repo.

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freasy commented May 2, 2023

@SteveCEvans is this ready to merge?

EDIT - SPI DMA: If bus is shared we need to assign manual:

#define SPI_RX_DMA_OPT 6
#define SPI_TX_DMA_OPT 7
#define SPI_RX_DMA_OPT 8
#define SPI_TX_DMA_OPT 9

These definitions are meaningless.

@haslinghuis copied wrong 😅

@SteveCEvans SteveCEvans mentioned this pull request May 2, 2023
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github-actions bot commented May 2, 2023

Do you want to test this code? Here you have an automated build:
Assets
WARNING: It may be unstable. Use only for testing! See: https://www.youtube.com/watch?v=I1uN9CN30gw for instructions for unified targets!

@haslinghuis haslinghuis added this to the 4.5 milestone May 2, 2023
@haslinghuis haslinghuis merged commit 9ff4723 into betaflight:master May 10, 2023
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haslinghuis pushed a commit to haslinghuis/betaflight that referenced this pull request May 10, 2023
@SteveCEvans @haslinghuis
If CS is asserted between transfers then consider bus to be busy for …
c5c894e 
…all but owning device (betaflight#12604)

* If CS is asserted between transfers then consider bus to be busy for all but owning device

* Track if MAX7456 is mid DMA transfer, not simply that the SPI bus is busy

* Enable SPI DMA TX/RX together
@haslinghuis haslinghuis mentioned this pull request May 10, 2023
Merged
haslinghuis added a commit that referenced this pull request May 12, 2023
@haslinghuis @SteveCEvans
[4.4.2] If CS is asserted between transfers then consider bus to be b…
167bd0f 
…usy for … (#12784)

If CS is asserted between transfers then consider bus to be busy for all but owning device (#12604)

* If CS is asserted between transfers then consider bus to be busy for all but owning device

* Track if MAX7456 is mid DMA transfer, not simply that the SPI bus is busy

* Enable SPI DMA TX/RX together

Co-authored-by: Steve Evans <SteveCEvans@users.noreply.github.com>
AkankshaJjw pushed a commit to AkankshaJjw/betaflight that referenced this pull request May 29, 2023
@SteveCEvans @AkankshaJjw
If CS is asserted between transfers then consider bus to be busy for …
5f29f8a 
…all but owning device (betaflight#12604)

* If CS is asserted between transfers then consider bus to be busy for all but owning device

* Track if MAX7456 is mid DMA transfer, not simply that the SPI bus is busy

* Enable SPI DMA TX/RX together
@Star4fish
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Star4fish commented Jun 4, 2023 •
edited

#define SPI1_RX_DMA_OPT 6
#define SPI1_TX_DMA_OPT 7
#define SPI2_RX_DMA_OPT 8
#define SPI2_TX_DMA_OPT 9

not working for speedybee f405 v3

edit
update to 4.5.0 doesn't resolve the issue

davidbitton pushed a commit to davidbitton/betaflight that referenced this pull request Feb 5, 2024
@SteveCEvans @davidbitton
If CS is asserted between transfers then consider bus to be busy for …
522d1c1 
…all but owning device (betaflight#12604)

* If CS is asserted between transfers then consider bus to be busy for all but owning device

* Track if MAX7456 is mid DMA transfer, not simply that the SPI bus is busy

* Enable SPI DMA TX/RX together
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@freasy freasy freasy approved these changes

@haslinghuis haslinghuis haslinghuis approved these changes

@sugaarK sugaarK sugaarK approved these changes

@blckmn blckmn Awaiting requested review from blckmn

@KarateBrot KarateBrot Awaiting requested review from KarateBrot

@klutvott123 klutvott123 Awaiting requested review from klutvott123

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Labels
Ready to Merge RN: BUGFIX
Projects
Finalizing Firmware 4.5 Release
Status: COMPLETED
Milestone
4.5
Development

Successfully merging this pull request may close these issues.

Blackbox logging issue on SpeedyBee F405 V3, possibly due to sharing SPI bus with analog OSD
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@SteveCEvans @blckmn @haslinghuis @freasy @Star4fish @sugaarK