STM32F7: Enabled cache #3422

blckmn · 2017-07-03T07:04:44Z

No description provided.

martinbudden · 2017-07-04T17:12:17Z

@blckmn , you seem to be enabling the I-Cache but not the D-Cache. Is that correct, and, if so, why?

blckmn · 2017-07-04T18:32:13Z

D cache needs serious consideration about cache write backs etc. Need to define regions it is not enabled on or has write through, due to dma.

I cache is just instructions.

hydra · 2017-07-07T17:23:02Z

@blckmn shouldn't the stm32_flash_f722.ld reference stm32_flash_f7_split.ld instead of stm32_flash_split.ld ?

hydra · 2017-07-07T17:33:22Z

when the f722 linker script is updated to use the *_f7_split.ld, which is the only code I've seen that references the ITCMFL / ITCMFL1 regions the system fails to initialise.

hydra · 2017-07-07T20:25:16Z

I did a bit of testing since the ICache seems to be unrelated to the other changes in this PR and have some findings for you:

with ICache enabled

# tasks
Task list             rate/hz  max/us  avg/us maxload avgload     total/ms
00 - (         SYSTEM)      9       2       1    0.5%    0.5%         1
01 - (            PID)   1908      78      43   15.3%    8.7%     41409
   - (           GYRO)   7633
02 - (          ACCEL)    975      33      18    3.7%    2.2%      2239
03 - (       ATTITUDE)     99      23      17    0.7%    0.6%       207
04 - (             RX)     49      64      45    0.8%    0.7%       313
05 - (         SERIAL)    100     373       2    4.2%    0.5%       299
07 - (BATTERY_VOLTAGE)     49       5       2    0.5%    0.5%        15
08 - (BATTERY_CURRENT)     50       3       1    0.5%    0.5%         6
09 - ( BATTERY_ALERTS)      4      12       3    0.5%    0.5%         1
10 - (         BEEPER)    100      16       2    0.6%    0.5%        17
13 - (           BARO)     43     112      69    0.9%    0.7%       372
14 - (       ALTITUDE)     40      24      14    0.5%    0.5%        72
16 - (      TELEMETRY)    249      20       3    0.9%    0.5%       216
17 - (       LEDSTRIP)    100      62      37    1.1%    0.8%       398
18 - (            OSD)     59    1698     107   10.5%    1.1%       877
20 - (            CMS)     59       8       2    0.5%    0.5%         9
21 - (        VTXCTRL)      4       2       1    0.5%    0.5%         0
RX Check Function                  12       2                        15
Total (excluding SERIAL)                        38.0%   19.3%

with ICache disabled

# tasks
Task list             rate/hz  max/us  avg/us maxload avgload     total/ms
00 - (         SYSTEM)      9       3       1    0.5%    0.5%         0
01 - (            PID)   1968     121      66   24.3%   13.4%     12834
   - (           GYRO)   7874
02 - (          ACCEL)    957      48      28    5.0%    3.1%       744
03 - (       ATTITUDE)     98      38      24    0.8%    0.7%        65
04 - (             RX)     49     117      88    1.0%    0.9%       134
05 - (         SERIAL)     99     497       2    5.4%    0.5%        88
07 - (BATTERY_VOLTAGE)     49       9       3    0.5%    0.5%         4
08 - (BATTERY_CURRENT)     49       6       2    0.5%    0.5%         1
09 - ( BATTERY_ALERTS)      4       5       3    0.5%    0.5%         0
10 - (         BEEPER)     99      11       2    0.6%    0.5%         5
13 - (           BARO)     43     108      69    0.9%    0.7%        84
14 - (       ALTITUDE)     39      29      18    0.6%    0.5%        19
16 - (      TELEMETRY)    246      25       5    1.1%    0.6%        63
17 - (       LEDSTRIP)     98     231     130    2.7%    1.7%       368
18 - (            OSD)     59    2610     220   15.8%    1.7%       346
20 - (            CMS)     59       4       2    0.5%    0.5%         2
21 - (        VTXCTRL)      4       4       1    0.5%    0.5%         0
RX Check Function                   9       5                         7
Total (excluding SERIAL)                        55.8%   26.8%

hydra · 2017-07-09T11:11:19Z

stm32_flash_f7_split.ld is still unused.

blckmn · 2017-07-09T18:40:26Z

@hydra I know :) it's there for testing. In the existing F722 script you can replace the standard split with the F7 split. I'm still reading up on the MCU and seeing what gives the best performance

blckmn · 2017-07-10T04:40:57Z

Still playing with this, and unsure if I have this right yet.

To enable you need to build with EXTRA_FLAGS=-DUSE_ITCM_RAM added to command line.

e.g. make TARGET=NERO EXTRA_FLAGS=-DUSE_ITCM_RAM

ledvinap · 2017-07-10T08:20:43Z

src/main/fc/fc_init.c

@@ -240,6 +240,12 @@ void spiPreInit(void)

 void init(void)
 {
+    /* Load functions into ITCM RAM */ 


Isn't this code CPU specific?

ledvinap · 2017-07-10T08:22:01Z

src/main/target/common_fc_pre.h

@@ -76,6 +76,12 @@
 #define DEFAULT_AUX_CHANNEL_COUNT       6
 #endif

+#ifdef USE_ITCM_RAM
+#define CRITICAL_SECTION __attribute__((section(".critical_code")))


CRITICAL_SECTION is very confusing name (https://en.wikipedia.org/wiki/Critical_section)

Agreed. My first thought when hearing the term Critical Section is the definition @ledvinap points to.

While I generally have a preference for logical names rather than physical names, I can't think of a good logical name. So I suggest we use the name ITCM_SECTION - at least that has the benefit that it is clear to a reader what is going on.

hydra · 2017-07-10T12:48:20Z

i'll give the updated code a try soon.

… targets with USE_ITCM_RAM defined.

martinbudden · 2017-07-16T09:42:24Z

@blckmn , what's the status of this PR?

blckmn changed the title ~~Enabled cache, and cleaned up formatting in system file.~~ STM32F7: Enabled cache Jul 3, 2017

martinbudden added the Rebase Required label Jul 5, 2017

blckmn force-pushed the f7_cacheenable branch from aabcfe7 to 7bc3981 Compare July 8, 2017 21:31

blckmn removed the Rebase Required label Jul 8, 2017

mikeller added this to the Betaflight v3.2 milestone Jul 9, 2017

hydra added Don't Merge In Development labels Jul 9, 2017

blckmn force-pushed the f7_cacheenable branch from 7bc3981 to bf7d6ec Compare July 9, 2017 20:41

Created ITCM RAM to move high speed code into for execution

7a8a2d1

blckmn force-pushed the f7_cacheenable branch from 9cf657c to 7a8a2d1 Compare July 10, 2017 04:39

Copy code to ITCM_RAM

ff01735

blckmn force-pushed the f7_cacheenable branch from 8317bf5 to ff01735 Compare July 10, 2017 05:36

ledvinap reviewed Jul 10, 2017

View reviewed changes

blckmn force-pushed the f7_cacheenable branch from d17caad to bc74e90 Compare July 10, 2017 10:00

Renamed based on suggestions, added DEF to ensure tcm only applies to…

dd06b59

… targets with USE_ITCM_RAM defined.

blckmn force-pushed the f7_cacheenable branch from aa88038 to dd06b59 Compare July 11, 2017 08:47

martinbudden added the Rebase Required label Jul 31, 2017

martinbudden modified the milestones: Betaflight v3.3, Betaflight v3.2 Aug 1, 2017

blckmn closed this Dec 22, 2017

blckmn deleted the f7_cacheenable branch December 22, 2017 04:06

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STM32F7: Enabled cache #3422

STM32F7: Enabled cache #3422

blckmn commented Jul 3, 2017

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blckmn commented Jul 4, 2017

hydra commented Jul 7, 2017

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hydra commented Jul 9, 2017

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ledvinap Jul 10, 2017

ledvinap Jul 10, 2017

martinbudden Jul 10, 2017

hydra commented Jul 10, 2017

martinbudden commented Jul 16, 2017

STM32F7: Enabled cache #3422

STM32F7: Enabled cache #3422

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blckmn commented Jul 3, 2017

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