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After a big break and mentally going over things that need to be debugged and issues I'm having, mostly related to PCIe, I have decided to put this project to sleep and start a new intermediate project called FejkonX.
The difference will be that FejkonX will use a static 3x SFP+ ports, 2x FC8 and 1x 10G Ethernet. No PCIe. It will support capturing/mirroring FC traffic as well as sending/receiving it over Ethernet. TX pacing will be left to the Ethernet sender as it would have to implement an FC stack anyway.
This should significantly decrease the complexity of Fejkon and provide a nice middle ground to get something real up and running.
The same IP cores related to FC and such will of course be reused.
The text was updated successfully, but these errors were encountered:
After a big break and mentally going over things that need to be debugged and issues I'm having, mostly related to PCIe, I have decided to put this project to sleep and start a new intermediate project called FejkonX.
The difference will be that FejkonX will use a static 3x SFP+ ports, 2x FC8 and 1x 10G Ethernet. No PCIe. It will support capturing/mirroring FC traffic as well as sending/receiving it over Ethernet. TX pacing will be left to the Ethernet sender as it would have to implement an FC stack anyway.
This should significantly decrease the complexity of Fejkon and provide a nice middle ground to get something real up and running.
The same IP cores related to FC and such will of course be reused.
The text was updated successfully, but these errors were encountered: