kernel: i2c: Fix the SMBus example

I2C/SMBus do not support two Start bits in the same sequence. It is
actually a repeated start (abbreviated Sr) which must be performed after
the command byte to signify that we change the direction of the flow:
the host wrote the command, now it's the peripheral responsibility to
talk on the bus.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

slides/kernel-i2c/kernel-i2c.tex

@@ -374,7 +374,7 @@ \section{Introduction to the I2C subsystem}
     to read one byte of data from a device ``register''.
     \begin{itemize}
     \item It does the following operations:
-      \code{S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P}
+      \code{S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P}
     \item Which means it first writes a one byte data command ({\em
         Comm}, which is the ``register'' address), and then reads
       back one byte of data ({\em [Data]}).