Consistent naming of the RISC-V architecture

Signed-off-by: Michael Opdenacker <michael.opdenacker@bootlin.com>
bootlin · Mar 8, 2021 · 50ae6fa · 50ae6fa
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diff --git a/slides/sysdev-embedded-linux/sysdev-embedded-linux.tex b/slides/sysdev-embedded-linux/sysdev-embedded-linux.tex
@@ -1424,7 +1424,7 @@ \subsection{System building}
     \item But probably too costly to maintain
           and unnecessarily big for production systems.
     \item Available on multiple architectures: ARM (\code{armel},
-          \code{armhf}, \code{arm64}), MIPS, PowerPC, RiscV (in progress)...
+          \code{armhf}, \code{arm64}), MIPS, PowerPC, RISC-V (in progress)...
     \item Software is compiled natively by default.
     \item Use the \code{debootstrap} command to build a root
           filesystem for your architecture, with a custom selection

diff --git a/slides/sysdev-intro/sysdev-intro.tex b/slides/sysdev-intro/sysdev-intro.tex
@@ -233,7 +233,7 @@ \subsection{Embedded hardware for Linux systems}
     (multimedia, industrial)
   \item ARM, with hundreds of different {\em System on Chip}s ({\em
 	SoC}: CPU + on-chip devices, for all sorts of products)
-  \item RiscV, the rising architecture with a free instruction set
+  \item RISC-V, the rising architecture with a free instruction set
         (from high-end cloud computing to the smallest embedded systems)
   \item PowerPC (mainly real-time, industrial applications)
   \item MIPS (mainly networking applications)