Designs Verification

Here you can find different verifications, time analysis, etc.

University of Costa Rica

August, 2020

Projects:

1. Timing_Design [Verilog]

This project consists of designing a behavioral description of a counter for which a synthesis analysis will be carried out in order to visualize the different aspects of timing

2. Functional_Verification [Verilog]

Functional verification of three counters in order to guarantee the correct operation of the designs.

3. Power_analysis [Verilog]

This task consists of analyzing the power consumption of three different adders.

4. Qflow_Analysis [Qflow]

Aspects analyzed:

• Frequency.

• Area.

• Number and type of gates.

• Path delays.

• Place and route.

5. Desing_Complete_Process [Verilog] [Qflow] [Electric] [Spice]

Complete process of the design of a 4 bit and 32 bits counters in order to guarantee the correct operation of the designs.