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Components that do a single read/write to a seq_mem
generate circular combinational logic
#1963
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@nathanielnrn, can you try dumping out the version of the program from lowering I will not have any debugging cycles so please take a shot and let me know what you learn. I can try to provide async help. |
seq_mem
generate circular combinational logicseq_mem
generate circular combinational logic
seq_mem
generate circular combinational logicseq_mem
generate circular combinational logic
Just posting some updates as I find them. If we disable optimizations the following program also does not simulate (with optimizations this is fine). It produces an error similar to that in the original issue:
With the following error
However, the same program with the
So perhaps something is going wrong in some control sequence pass? |
The following program, when run through fud with
fud e <program> --from calyx --to vcd --through verilog
creates a circular combinational logic error (Simulating withicarus-verilog
just hangs):The program in question:
This does not happen if the reader and writer components both have another group thats reads/writes to the second address of the
seq_mem_d1
. i.e the program listed in this comment of #1955.cc @rachitnigam
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