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Generate Verilog from Atomicc IR files (which are generated from llvm-translate)
Branch of llvm repository. Use branch release_34atomicc1
Mirror of official clang git repository located at http://llvm.org/git/clang. Updated every five minutes.
Connectal is a framework for software-driven hardware development.
Memoizes execution of build commands
A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
Generates Makefiles to synthesize, place, and route verilog using Vivado
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
C++ standards drafts
Mirror of tachyon-da cvc Verilog simulator
A fork of the main Verilator project for development work.
llvm runtime interpreter/translator
connectal (formerly called xbsv) contains a utility to generate bit files for Xilinx Zynq devices from BSV programs.
packaging branch of openocd
Repository for publishing non-jekyll documentation
Python Productivity for ZYNQ with Python board level designs
Bluespec-derived HDL based on Dart
The official Linux kernel from Xilinx
RISC-V Linux Port
RISC-V Proxy Kernel
QEMU with RISC-V Emulation Support
Scripts to create a boot.bin file for linux on Xilinx Zync
KLEE Symbolic Virtual Machine
Scripts for common operations, dependent on local device configuration
A minimalistic and high-performance SAT solver