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| Original file line number | Diff line number | Diff line change |
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| </messages> | ||
|
|
124 changes: 124 additions & 0 deletions
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boards/digilent-xc3s500e/synthesis/build/_xmsgs/map.xmsgs
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| <msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">phy_mii_data_IBUF</arg> has no load. | ||
| </msg> | ||
|
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||
| <msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">10</arg> more times for the following (max. 5 shown): | ||
| <arg fmt="%s" index="3">phy_tx_clk_IBUF, | ||
| phy_col_IBUF, | ||
| phy_crs_IBUF, | ||
| uart_rx_mon_IBUF, | ||
| phy_dv_IBUF</arg> | ||
| To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch. | ||
| </msg> | ||
|
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||
| <msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set. | ||
| </msg> | ||
|
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| <msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">clkin</arg> are pushed forward through input buffer. | ||
| </msg> | ||
|
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| <msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">phy_tx_clk</arg> are pushed forward through input buffer. | ||
| </msg> | ||
|
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| <msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">phy_rx_clk</arg> are pushed forward through input buffer. | ||
| </msg> | ||
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| <msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. | ||
| </msg> | ||
|
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| <msg type="warning" file="LIT" num="176" delta="old" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol "physical_group_sys_clk/b1" (output signal=sys_clk)</arg> has a mix of clock and non-clock loads. The non-clock loads are: | ||
| <arg fmt="%s" index="2">Pin PSCLK of ddram/clkgen_dqs</arg> | ||
| </msg> | ||
|
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| <msg type="warning" file="LIT" num="175" delta="old" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol "physical_group_sys_clk_n/b2" (output signal=sys_clk_n)</arg> has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed): | ||
| <arg fmt="%s" index="2">Pin I0 of ddram/hpdmc/ddrio/oddr_dqm/oddr1/Mmux_Q11 | ||
| Pin I0 of ddram/hpdmc/ddrio/oddr_dqm/oddr0/Mmux_Q11 | ||
| Pin I0 of ddram/hpdmc/ddrio/sdram_dq_t<0>1 | ||
| Pin I0 of ddram/hpdmc/ddrio/oddr_dq/oddr9/Mmux_Q11 | ||
| Pin I0 of ddram/hpdmc/ddrio/oddr_dq/oddr8/Mmux_Q11</arg> | ||
| </msg> | ||
|
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||
| <msg type="warning" file="LIT" num="178" delta="old" >Clock buffer <arg fmt="%s" index="1">BUFGMUX symbol "physical_group_ddram/dqs_clk_n/ddram/b2" (output signal=ddram/dqs_clk_n)</arg> does not drive clock loads. Driving only non-clock loads with a clock buffer will cause ALL of the dedicated clock routing resources for this buffer to be wasted. The non-clock loads are: | ||
| <arg fmt="%s" index="2">Pin I0 of ddram/hpdmc/ddrio/sdram_dqs_out<0>1</arg> | ||
| </msg> | ||
|
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| <msg type="warning" file="Pack" num="266" delta="old" >The function generator <arg fmt="%s" index="1">cpu/cpu/adder/addsub/Result<0>1</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/cpu/x_result<0>100_f5</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">lcd/busy_data_and0000</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_rx_data<0>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_rx_data<1>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_rx_data<2>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_rx_data<3>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_rx_clk_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_tx_clk_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_col_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_crs_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">uart_rx_mon_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="368" delta="old" >The signal <<arg fmt="%s" index="1">uart_tx_mon_OBUF</arg>> is incomplete. The signal is not driven by any source pin in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_dv_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">phy_mii_data_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="781" delta="old" ><arg fmt="%s" index="1">PULLUP</arg> on an active net. <arg fmt="%s" index="2">PULLUP</arg> of comp <arg fmt="%s" index="3">led<7></arg> is set but the tri state is not configured. | ||
| </msg> | ||
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| <msg type="info" file="PhysDesignRules" num="772" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">clkgen</arg>, consult the device Interactive Data Sheet. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="1063" delta="old" >Invalid configuration (incorrect pin connections and/or modes) on block:<<arg fmt="%s" index="1">cpu/cpu/instruction_unit/icache/memories[1].way_0_data_ram/Mram_mem1.A</arg>>:<<arg fmt="%s" index="2">RAMB16_RAMB16A</arg>>. The block is configured to use an input parity pins. There is a dangling output parity pin. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="1063" delta="old" >Invalid configuration (incorrect pin connections and/or modes) on block:<<arg fmt="%s" index="1">cpu/cpu/instruction_unit/icache/memories[1].way_0_data_ram/Mram_mem2.A</arg>>:<<arg fmt="%s" index="2">RAMB16_RAMB16A</arg>>. The block is configured to use an input parity pins. There is a dangling output parity pin. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="1063" delta="old" >Invalid configuration (incorrect pin connections and/or modes) on block:<<arg fmt="%s" index="1">cpu/cpu/instruction_unit/icache/memories[1].way_0_data_ram/Mram_mem3.A</arg>>:<<arg fmt="%s" index="2">RAMB16_RAMB16A</arg>>. The block is configured to use an input parity pins. There is a dangling output parity pin. | ||
| </msg> | ||
|
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||
| <msg type="warning" file="PhysDesignRules" num="1063" delta="old" >Invalid configuration (incorrect pin connections and/or modes) on block:<<arg fmt="%s" index="1">cpu/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem1.A</arg>>:<<arg fmt="%s" index="2">RAMB16_RAMB16A</arg>>. The block is configured to use an input parity pins. There is a dangling output parity pin. | ||
| </msg> | ||
|
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||
| <msg type="warning" file="PhysDesignRules" num="1063" delta="old" >Invalid configuration (incorrect pin connections and/or modes) on block:<<arg fmt="%s" index="1">cpu/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem2.A</arg>>:<<arg fmt="%s" index="2">RAMB16_RAMB16A</arg>>. The block is configured to use an input parity pins. There is a dangling output parity pin. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="1063" delta="old" >Invalid configuration (incorrect pin connections and/or modes) on block:<<arg fmt="%s" index="1">cpu/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem3.A</arg>>:<<arg fmt="%s" index="2">RAMB16_RAMB16A</arg>>. The block is configured to use an input parity pins. There is a dangling output parity pin. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="738" delta="old" >Unexpected DCM configuration. DCM comp <arg fmt="%s" index="1">ddram/clkgen_dqs</arg> has CLKOUT_PHASE_SHIFT set without a connection from CLKO or CLK2X to CLKFB. To achieve fine-grained phase shifting (CLKOUT_PHASE_SHIFT = FIXED or VARIABLE), CLKFB must be connected to either CLK0 or CLK2X. | ||
| </msg> | ||
|
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| <msg type="warning" file="PhysDesignRules" num="739" delta="old" >Unexpected DCM feedback loop. The signal <arg fmt="%s" index="1">ddram/dqs_clk</arg> on the CLKFB pin of comp <arg fmt="%s" index="2">ddram/clkgen_dqs</arg> is not driven by an IOB or BUFGMUX therefore the phase relationship of output clocks to CLKIN cannot be guaranteed. | ||
| </msg> | ||
|
|
||
| </messages> | ||
|
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43 changes: 43 additions & 0 deletions
43
boards/digilent-xc3s500e/synthesis/build/_xmsgs/ngdbuild.xmsgs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,43 @@ | ||
| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| <msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1"><NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";> [system.ucf(230)]</arg>: No appropriate instances for the TNM constraint are driven by "<arg fmt="%s" index="2">phy_rx_clk</arg>". | ||
| </msg> | ||
|
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| <msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1"><NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";> [system.ucf(231)]</arg>: No appropriate instances for the TNM constraint are driven by "<arg fmt="%s" index="2">phy_tx_clk</arg>". | ||
| </msg> | ||
|
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| <msg type="warning" file="ConstraintSystem" num="56" delta="old" >Constraint <arg fmt="%s" index="1"><TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;> [system.ucf(232)]</arg>: Unable to find an active <arg fmt="%s" index="2">'TimeGrp' or 'TNM' or 'TPSync'</arg> constraint named '<arg fmt="%s" index="3">TXCLK_GRP</arg>'. | ||
| </msg> | ||
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| <msg type="warning" file="ConstraintSystem" num="56" delta="old" >Constraint <arg fmt="%s" index="1"><TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;> [system.ucf(233)]</arg>: Unable to find an active <arg fmt="%s" index="2">'TimeGrp' or 'TNM' or 'TPSync'</arg> constraint named '<arg fmt="%s" index="3">RXCLK_GRP</arg>'. | ||
| </msg> | ||
|
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| <msg type="warning" file="ConstraintSystem" num="193" delta="old" >The <arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">RXCLK_GRP</arg>', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing <arg fmt="%s" index="3">MaxDelay</arg> constraint '<arg fmt="%s" index="4">TSRXIN</arg>'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: | ||
| <arg fmt="%s" index="5"><TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;> [system.ucf(233)] | ||
| </arg></msg> | ||
|
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| <msg type="warning" file="ConstraintSystem" num="197" delta="old" >The following specification is invalid because the referenced TNM constraint was removed: | ||
| <arg fmt="%s" index="1"><TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;> [system.ucf(233)]</arg> | ||
| </msg> | ||
|
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| <msg type="warning" file="ConstraintSystem" num="193" delta="old" >The <arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">TXCLK_GRP</arg>', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing <arg fmt="%s" index="3">MaxDelay</arg> constraint '<arg fmt="%s" index="4">TSTXOUT</arg>'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: | ||
| <arg fmt="%s" index="5"><TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;> [system.ucf(232)] | ||
| </arg></msg> | ||
|
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| <msg type="warning" file="ConstraintSystem" num="197" delta="old" >The following specification is invalid because the referenced TNM constraint was removed: | ||
| <arg fmt="%s" index="1"><TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;> [system.ucf(232)]</arg> | ||
| </msg> | ||
|
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| <msg type="warning" file="NgdBuild" num="478" delta="old" >clock net <arg fmt="%s" index="1">ddram/dqs_clk_n</arg> with clock driver <arg fmt="%s" index="2">ddram/b2</arg> drives no clock pins | ||
| </msg> | ||
|
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| <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net '<arg fmt="%s" index="2">phy_mii_data</arg>' has no legal driver | ||
| </msg> | ||
|
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| </messages> | ||
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