[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:27:-`include "el2_param.vh" design/ifu/el2_ifu_mem_ctl.sv:28:- ) design/ifu/el2_ifu_mem_ctl.sv:29:- ( design/ifu/el2_ifu_mem_ctl.sv:30:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/ifu/el2_ifu_mem_ctl.sv:31:- input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/ifu/el2_ifu_mem_ctl.sv:32:- input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. design/ifu/el2_ifu_mem_ctl.sv:33:- input logic rst_l, // reset, active low design/ifu/el2_ifu_mem_ctl.sv:34:- design/ifu/el2_ifu_mem_ctl.sv:35:- input logic exu_flush_final, // Flush from the pipeline., includes flush lower design/ifu/el2_ifu_mem_ctl.sv:36:- input logic dec_tlu_flush_lower_wb, // Flush lower from the pipeline. design/ifu/el2_ifu_mem_ctl.sv:37:- input logic dec_tlu_flush_err_wb, // Flush from the pipeline due to perr. design/ifu/el2_ifu_mem_ctl.sv:38:- input logic dec_tlu_i0_commit_cmt, // committed i0 instruction design/ifu/el2_ifu_mem_ctl.sv:39:- input logic dec_tlu_force_halt, // force halt. design/ifu/el2_ifu_mem_ctl.sv:40:- design/ifu/el2_ifu_mem_ctl.sv:41:- input logic [31:1] ifc_fetch_addr_bf, // Fetch Address byte aligned always. F1 stage. design/ifu/el2_ifu_mem_ctl.sv:42:- input logic ifc_fetch_uncacheable_bf, // The fetch request is uncacheable space. F1 stage design/ifu/el2_ifu_mem_ctl.sv:43:- input logic ifc_fetch_req_bf, // Fetch request. Comes with the address. F1 stage design/ifu/el2_ifu_mem_ctl.sv:44:- input logic ifc_fetch_req_bf_raw, // Fetch request without some qualifications. Used for clock-gating. F1 stage design/ifu/el2_ifu_mem_ctl.sv:45:- input logic ifc_iccm_access_bf, // This request is to the ICCM. Do not generate misses to the bus. design/ifu/el2_ifu_mem_ctl.sv:46:- input logic ifc_region_acc_fault_bf, // Access fault. in ICCM region but offset is outside defined ICCM. design/ifu/el2_ifu_mem_ctl.sv:47:- input logic ifc_dma_access_ok, // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle). design/ifu/el2_ifu_mem_ctl.sv:48:- input logic dec_tlu_fence_i_wb, // Fence.i instruction is committing. Clear all Icache valids. design/ifu/el2_ifu_mem_ctl.sv:49:- input logic ifu_bp_hit_taken_f, // Branch is predicted taken. Kill the fetch next cycle. design/ifu/el2_ifu_mem_ctl.sv:50:- design/ifu/el2_ifu_mem_ctl.sv:51:- input logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified design/ifu/el2_ifu_mem_ctl.sv:52:- design/ifu/el2_ifu_mem_ctl.sv:53:- output logic ifu_miss_state_idle, // No icache misses are outstanding. design/ifu/el2_ifu_mem_ctl.sv:54:- output logic ifu_ic_mb_empty, // Continue with normal fetching. This does not mean that miss is finished. design/ifu/el2_ifu_mem_ctl.sv:55:- output logic ic_dma_active , // In the middle of servicing dma request to ICCM. Do not make any new requests. design/ifu/el2_ifu_mem_ctl.sv:56:- output logic ic_write_stall, // Stall fetch the cycle we are writing th

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:907:-///////////////////////////////////////////////////////////////////////////////////// design/ifu/el2_ifu_mem_ctl.sv:908:-// Parity checking logic for Icache logic. // design/ifu/el2_ifu_mem_ctl.sv:909:-///////////////////////////////////////////////////////////////////////////////////// design/ifu/el2_ifu_mem_ctl.sv:1045:+ ///////////////////////////////////////////////////////////////////////////////////// design/ifu/el2_ifu_mem_ctl.sv:1046:+ // Parity checking logic for Icache logic. // design/ifu/el2_ifu_mem_ctl.sv:1047:+ /////////////////////////////////////////////////////////////////////////////////////

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:921:- assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}} ; design/ifu/el2_ifu_mem_ctl.sv:922:- assign iccm_correct_ecc = (perr_state == ECC_CORR); design/ifu/el2_ifu_mem_ctl.sv:923:- assign dma_sb_err_state = (perr_state == DMA_SB_ERR); design/ifu/el2_ifu_mem_ctl.sv:924:- assign iccm_buf_correct_ecc = iccm_correct_ecc & ~dma_sb_err_state_ff; design/ifu/el2_ifu_mem_ctl.sv:1059:+ assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}}; design/ifu/el2_ifu_mem_ctl.sv:1060:+ assign iccm_correct_ecc = (perr_state == ECC_CORR); design/ifu/el2_ifu_mem_ctl.sv:1061:+ assign dma_sb_err_state = (perr_state == DMA_SB_ERR); design/ifu/el2_ifu_mem_ctl.sv:1062:+ assign iccm_buf_correct_ecc = iccm_correct_ecc & ~dma_sb_err_state_ff;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:935:- // FIFO state machine design/ifu/el2_ifu_mem_ctl.sv:936:- always_comb begin : ERROR_SM design/ifu/el2_ifu_mem_ctl.sv:937:- perr_nxtstate = ERR_IDLE; design/ifu/el2_ifu_mem_ctl.sv:938:- perr_state_en = 1'b0; design/ifu/el2_ifu_mem_ctl.sv:939:- perr_sel_invalidate = 1'b0; design/ifu/el2_ifu_mem_ctl.sv:1073:+ // FIFO state machine design/ifu/el2_ifu_mem_ctl.sv:1074:+ always_comb begin : ERROR_SM design/ifu/el2_ifu_mem_ctl.sv:1075:+ perr_nxtstate = ERR_IDLE; design/ifu/el2_ifu_mem_ctl.sv:1076:+ perr_state_en = 1'b0; design/ifu/el2_ifu_mem_ctl.sv:1077:+ perr_sel_invalidate = 1'b0;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:978:- end design/ifu/el2_ifu_mem_ctl.sv:979:- design/ifu/el2_ifu_mem_ctl.sv:980:- rvdffs #(($bits(perr_state_t))) perr_state_ff (.clk(active_clk), .din(perr_nxtstate), .dout({perr_state}), .en(perr_state_en), .*); design/ifu/el2_ifu_mem_ctl.sv:981:- design/ifu/el2_ifu_mem_ctl.sv:982:- //////////////////////////////////// Create stop fetch State Machine ///////////////////////// design/ifu/el2_ifu_mem_ctl.sv:983:- //////////////////////////////////// Create stop fetch State Machine ///////////////////////// design/ifu/el2_ifu_mem_ctl.sv:984:- //////////////////////////////////// Create stop fetch State Machine ///////////////////////// design/ifu/el2_ifu_mem_ctl.sv:985:- //////////////////////////////////// Create stop fetch State Machine ///////////////////////// design/ifu/el2_ifu_mem_ctl.sv:986:- //////////////////////////////////// Create stop fetch State Machine ///////////////////////// design/ifu/el2_ifu_mem_ctl.sv:987:- always_comb begin : ERROR_STOP_FETCH design/ifu/el2_ifu_mem_ctl.sv:988:- err_stop_nxtstate = ERR_STOP_IDLE; design/ifu/el2_ifu_mem_ctl.sv:989:- err_stop_state_en = 1'b0; design/ifu/el2_ifu_mem_ctl.sv:990:- err_stop_fetch = 1'b0; design/ifu/el2_ifu_mem_ctl.sv:991:- iccm_correction_state = 1'b0; design/ifu/el2_ifu_mem_ctl.sv:992:- design/ifu/el2_ifu_mem_ctl.sv:993:- case (err_stop_state) design/ifu/el2_ifu_mem_ctl.sv:994:- ERR_STOP_IDLE: begin : err_stop_idle design/ifu/el2_ifu_mem_ctl.sv:995:- err_stop_nxtstate = ERR_FETCH1; design/ifu/el2_ifu_mem_ctl.sv:996:- err_stop_state_en = dec_tlu_flush_err_wb & (perr_state == ECC_WFF) & ~dec_tlu_force_halt; design/ifu/el2_ifu_mem_ctl.sv:997:- end design/ifu/el2_ifu_mem_ctl.sv:998:- ERR_FETCH1: begin : err_fetch1 // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state design/ifu/el2_ifu_mem_ctl.sv:999:- err_stop_nxtstate = (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr)) ? ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 : ERR_FETCH1; design/ifu/el2_ifu_mem_ctl.sv:1000:- err_stop_state_en = dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | ifu_fetch_val[0] | ifu_bp_hit_taken_q_f | dec_tlu_force_halt; design/ifu/el2_ifu_mem_ctl.sv:1001:- err_stop_fetch = ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr)) & ~(exu_flush_final | dec_tlu_i0_commit_cmt); design/ifu/el2_ifu_mem_ctl.sv:1002:- iccm_correction_state = 1'b1; design/ifu/el2_ifu_mem_ctl.sv:1116:+ end