Physical Memory Protection unit #119

koluckirafal · 2023-09-21T12:59:03Z

This PR adds Physical Memory Protection unit, compatible with RISC-V Privileged Architectures Machine-Level ISA specification. A minimal PMP software test is also added, which is used for veryfing if exceptions are properly raised on access violations. PyUVM-based tests are added as well.

github-actions · 2023-09-21T13:00:12Z

design/dec/el2_dec_pmp_ctl.sv

+   // [15:8] : PMP entry (x*4 + 1) configuration
+   //  [7:0] : PMP entry (x*4 + 0) configuration
+
+   localparam PMPCFG       = 12'h3a0;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Explicitly define a storage type for every parameter and localparam, (PMPCFG). [Style: constants] [explicit-parameter-storage-type]

github-actions · 2023-09-21T13:00:12Z

design/dec/el2_dec_pmp_ctl.sv

+   localparam PMPCFG       = 12'h3a0;
+
+   assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);
+   assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]

github-actions · 2023-09-21T13:00:12Z

design/dec/el2_dec_pmp_ctl.sv

+
+   for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff
+      rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk),
+                          .en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]

github-actions · 2023-09-21T13:00:12Z

design/dec/el2_dec_pmp_ctl.sv

+   for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff
+      rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk),
+                          .en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),
+                          .din(dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0] & 8'b10011111),


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]

github-actions · 2023-09-21T13:00:12Z

design/dec/el2_dec_pmp_ctl.sv

+   // NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping
+   //       to bits 33:32 of the physical address are always set to 0. (WARL)
+
+   localparam  PMPADDR0      = 12'h3b0;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Explicitly define a storage type for every parameter and localparam, (PMPADDR0). [Style: constants] [explicit-parameter-storage-type]

github-actions · 2023-09-21T13:00:15Z

design/lsu/el2_lsu_addrcheck.sv

+      if (pt.PMP_ENTRIES > 0) begin
+         assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                         // X. Address is in blocked region
+      end else begin
+         assign mpu_access_fault_d   = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok);                              // 3. Address is not in a populated non-dccm region


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 173 [Style: line-length] [line-length]

github-actions · 2023-09-21T13:00:15Z

design/lsu/el2_lsu_addrcheck.sv

   end else begin
      assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)                              |   // 0. Addr in dccm region but not in dccm offset
                                        (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)                                  |   // 0. Addr in dccm region but not in dccm offset
                                        (start_addr_in_pic_region_d & ~start_addr_in_pic_d)                                |   // 0. Addr in picm region but not in picm offset
                                        (end_addr_in_pic_region_d & ~end_addr_in_pic_d));                                      // 0. Addr in picm region but not in picm offset
-      assign mpu_access_fault_d      = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region
+      if (pt.PMP_ENTRIES > 0) begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2023-09-21T13:00:15Z

design/lsu/el2_lsu_addrcheck.sv

   end else begin
      assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)                              |   // 0. Addr in dccm region but not in dccm offset
                                        (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)                                  |   // 0. Addr in dccm region but not in dccm offset
                                        (start_addr_in_pic_region_d & ~start_addr_in_pic_d)                                |   // 0. Addr in picm region but not in picm offset
                                        (end_addr_in_pic_region_d & ~end_addr_in_pic_d));                                      // 0. Addr in picm region but not in picm offset
-      assign mpu_access_fault_d      = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region
+      if (pt.PMP_ENTRIES > 0) begin
+         assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                              // X. Address is in blocked region


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 161 [Style: line-length] [line-length]

github-actions · 2023-09-21T13:00:15Z

design/lsu/el2_lsu_addrcheck.sv

-      assign mpu_access_fault_d      = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region
+      if (pt.PMP_ENTRIES > 0) begin
+         assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                              // X. Address is in blocked region
+      end else begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2023-09-21T13:00:15Z

design/lsu/el2_lsu_addrcheck.sv

+      if (pt.PMP_ENTRIES > 0) begin
+         assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                              // X. Address is in blocked region
+      end else begin
+         assign mpu_access_fault_d   = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 178 [Style: line-length] [line-length]

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2023-09-21T13:00:13Z

design/dec/el2_dec.sv

@@ -286,6 +286,10 @@ import el2_pkg::*;

   output el2_trace_pkt_t  trace_rv_trace_pkt,      // trace packet


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet

input logic [15:0] ifu_i0_cinst, // 16b compressed instruction

github-actions · 2023-09-21T13:00:14Z

design/dec/el2_dec.sv

+   // PMP signals
+   output el2_pmp_cfg_pkt_t pmp_pmpcfg  [pt.PMP_ENTRIES],
+   output logic [31:0]      pmp_pmpaddr [pt.PMP_ENTRIES],


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// PMP signals

output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],

output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet

github-actions · 2023-09-21T13:00:14Z

design/dec/el2_dec_pmp_ctl.sv

+
+
+module el2_dec_pmp_ctl
+import el2_pkg::*;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import el2_pkg::*;

import el2_pkg::*;

github-actions · 2023-09-21T13:00:14Z

design/dec/el2_dec_pmp_ctl.sv

+   input logic free_l2clk,
+   input logic csr_wr_clk,
+   input logic rst_l,
+   input logic        dec_csr_wen_r_mod,  // csr write enable at wb
+   input logic [11:0] dec_csr_wraddr_r,   // write address for csr
+   input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
+   input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
+
+   input logic csr_pmpcfg,
+   input logic csr_pmpaddr0,
+   input logic csr_pmpaddr16,
+   input logic csr_pmpaddr32,
+   input logic csr_pmpaddr48,
+
+   input logic dec_pause_state, // Paused
+   input logic dec_tlu_pmu_fw_halted, // pmu/fw halted
+   input logic internal_dbg_halt_timers, // debug halted
+
+   output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data
+   output logic        dec_pmp_read_d, // pmp CSR address match
+
+   output el2_pmp_cfg_pkt_t pmp_pmpcfg  [pt.PMP_ENTRIES],
+   output logic [31:0]      pmp_pmpaddr [pt.PMP_ENTRIES],
+
+   input  logic        scan_mode
+   );
+
+   logic wr_pmpcfg_r;
+   logic [3:0] wr_pmpcfg_group;
+
+   logic wr_pmpaddr0_sel;
+   logic wr_pmpaddr16_sel;
+   logic wr_pmpaddr32_sel;
+   logic wr_pmpaddr48_sel;
+   logic wr_pmpaddr_r;
+   logic [1:0] wr_pmpaddr_quarter;
+   logic [5:0] wr_pmpaddr_address;
+
+   logic  [3:0] pmp_quarter_rdaddr;
+   logic [31:0] pmp_pmpcfg_rddata;
+
+   // ----------------------------------------------------------------------
+   // PMPCFGx (RW)
+   // [31:24] : PMP entry (x*4 + 3) configuration
+   // [23:16] : PMP entry (x*4 + 2) configuration
+   // [15:8] : PMP entry (x*4 + 1) configuration
+   //  [7:0] : PMP entry (x*4 + 0) configuration
+
+   localparam PMPCFG       = 12'h3a0;
+
+   assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);
+   assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)
+
+   for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff
+      rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk),
+                          .en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),
+                          .din(dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0] & 8'b10011111),
+                          .dout(pmp_pmpcfg[entry_idx]));
+   end
+
+   // ----------------------------------------------------------------------
+   // PMPADDRx (RW)
+   // [31:0] : PMP entry (x) address selector (word addressing)
+   //
+   // NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping
+   //       to bits 33:32 of the physical address are always set to 0. (WARL)
+
+   localparam  PMPADDR0      = 12'h3b0;
+   localparam PMPADDR16      = 12'h3c0;
+   localparam PMPADDR32      = 12'h3d0;
+   localparam PMPADDR48      = 12'h3e0;
+
+   assign wr_pmpaddr0_sel  = dec_csr_wraddr_r[11:4] ==  PMPADDR0[11:4];
+   assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4];
+   assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4];
+   assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4];
+   assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel);
+
+   assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel;
+   assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel;
+   assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address
+
+   for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
+      assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
+      rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
+                          .en(wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx) & (~pmp_pmpcfg[entry_idx].lock)),
+                          .din(dec_csr_wrdata_r[29:0]),
+                          .dout(pmp_pmpaddr[entry_idx][29:0]));
+   end
+
+   // CSR read mux
+
+   assign pmp_quarter_rdaddr     = dec_csr_rdaddr_d[3:0];
+   assign pmp_pmpcfg_rddata      = { pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}],
+                                     pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h2}],
+                                     pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h1}],
+                                     pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h0}]
+                                     };
+   assign dec_pmp_read_d         = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48;
+   assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}}    & pmp_pmpcfg_rddata) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`include "el2_param.vh"

)

(

input logic clk,

input logic free_l2clk,

input logic csr_wr_clk,

input logic rst_l,

input logic dec_csr_wen_r_mod, // csr write enable at wb

input logic [11:0] dec_csr_wraddr_r, // write address for csr

input logic [31:0] dec_csr_wrdata_r, // csr write data at wb

input logic [11:0] dec_csr_rdaddr_d, // read address for csr

input logic csr_pmpcfg,

input logic csr_pmpaddr0,

input logic csr_pmpaddr16,

input logic csr_pmpaddr32,

input logic csr_pmpaddr48,

input logic dec_pause_state, // Paused

input logic dec_tlu_pmu_fw_halted, // pmu/fw halted

input logic internal_dbg_halt_timers, // debug halted

output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data

output logic dec_pmp_read_d, // pmp CSR address match

output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],

input logic scan_mode

);

logic wr_pmpcfg_r;

logic [3:0] wr_pmpcfg_group;

logic wr_pmpaddr0_sel;

logic wr_pmpaddr16_sel;

logic wr_pmpaddr32_sel;

logic wr_pmpaddr48_sel;

logic wr_pmpaddr_r;

logic [1:0] wr_pmpaddr_quarter;

logic [5:0] wr_pmpaddr_address;

logic [3:0] pmp_quarter_rdaddr;

logic [31:0] pmp_pmpcfg_rddata;

// ----------------------------------------------------------------------

// PMPCFGx (RW)

// [31:24] : PMP entry (x*4 + 3) configuration

// [23:16] : PMP entry (x*4 + 2) configuration

// [15:8] : PMP entry (x*4 + 1) configuration

// [7:0] : PMP entry (x*4 + 0) configuration

localparam PMPCFG = 12'h3a0;

assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);

assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff

rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk),

.en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),

.din(dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0] & 8'b10011111),

.dout(pmp_pmpcfg[entry_idx]));

end

// ----------------------------------------------------------------------

// PMPADDRx (RW)

// [31:0] : PMP entry (x) address selector (word addressing)

//

// NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping

// to bits 33:32 of the physical address are always set to 0. (WARL)

localparam PMPADDR0 = 12'h3b0;

localparam PMPADDR16 = 12'h3c0;

localparam PMPADDR32 = 12'h3d0;

localparam PMPADDR48 = 12'h3e0;

assign wr_pmpaddr0_sel = dec_csr_wraddr_r[11:4] == PMPADDR0[11:4];

assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4];

assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4];

assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4];

assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel);

assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff

assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;

rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),

.en(wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx) & (~pmp_pmpcfg[entry_idx].lock)),

.din(dec_csr_wrdata_r[29:0]),

.dout(pmp_pmpaddr[entry_idx][29:0]));

end

// CSR read mux

assign pmp_quarter_rdaddr = dec_csr_rdaddr_d[3:0];

assign pmp_pmpcfg_rddata = { pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h2}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h1}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h0}]

};

assign dec_pmp_read_d = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48;

assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}} & pmp_pmpcfg_rddata) |

`include "el2_param.vh"

) (

input logic clk,

input logic free_l2clk,

input logic csr_wr_clk,

input logic rst_l,

input logic dec_csr_wen_r_mod, // csr write enable at wb

input logic [11:0] dec_csr_wraddr_r, // write address for csr

input logic [31:0] dec_csr_wrdata_r, // csr write data at wb

input logic [11:0] dec_csr_rdaddr_d, // read address for csr

input logic csr_pmpcfg,

input logic csr_pmpaddr0,

input logic csr_pmpaddr16,

input logic csr_pmpaddr32,

input logic csr_pmpaddr48,

input logic dec_pause_state, // Paused

input logic dec_tlu_pmu_fw_halted, // pmu/fw halted

input logic internal_dbg_halt_timers, // debug halted

output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data

output logic dec_pmp_read_d, // pmp CSR address match

output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

output logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],

input logic scan_mode

);

logic wr_pmpcfg_r;

logic [3:0] wr_pmpcfg_group;

logic wr_pmpaddr0_sel;

logic wr_pmpaddr16_sel;

logic wr_pmpaddr32_sel;

logic wr_pmpaddr48_sel;

logic wr_pmpaddr_r;

logic [1:0] wr_pmpaddr_quarter;

logic [5:0] wr_pmpaddr_address;

logic [3:0] pmp_quarter_rdaddr;

logic [31:0] pmp_pmpcfg_rddata;

// ----------------------------------------------------------------------

// PMPCFGx (RW)

// [31:24] : PMP entry (x*4 + 3) configuration

// [23:16] : PMP entry (x*4 + 2) configuration

// [15:8] : PMP entry (x*4 + 1) configuration

// [7:0] : PMP entry (x*4 + 0) configuration

localparam PMPCFG = 12'h3a0;

assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);

assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff

rvdffe #(8) pmpcfg_ff (

.*,

.clk (free_l2clk),

.en (wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),

.din (dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0] & 8'b10011111),

.dout(pmp_pmpcfg[entry_idx])

);

end

// ----------------------------------------------------------------------

// PMPADDRx (RW)

// [31:0] : PMP entry (x) address selector (word addressing)

//

// NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping

// to bits 33:32 of the physical address are always set to 0. (WARL)

localparam PMPADDR0 = 12'h3b0;

localparam PMPADDR16 = 12'h3c0;

localparam PMPADDR32 = 12'h3d0;

localparam PMPADDR48 = 12'h3e0;

assign wr_pmpaddr0_sel = dec_csr_wraddr_r[11:4] == PMPADDR0[11:4];

assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4];

assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4];

assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4];

assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel);

assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff

assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;

rvdffe #(30) pmpaddr_ff (

.*,

.clk (free_l2clk),

.en (wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx) & (~pmp_pmpcfg[entry_idx].lock)),

.din (dec_csr_wrdata_r[29:0]),

.dout(pmp_pmpaddr[entry_idx][29:0])

);

end

// CSR read mux

assign pmp_quarter_rdaddr = dec_csr_rdaddr_d[3:0];

assign pmp_pmpcfg_rddata = {

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h2}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h1}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h0}]

};

assign dec_pmp_read_d = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48;

assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}} & pmp_pmpcfg_rddata) |

github-actions · 2023-09-21T13:00:14Z

design/dec/el2_dec_pmp_ctl.sv

+                                     ({32{csr_pmpaddr48}} & pmp_pmpaddr[{2'h3, pmp_quarter_rdaddr}])
+                                     );
+
+endmodule // dec_pmp_ctl


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

endmodule // dec_pmp_ctl

endmodule // dec_pmp_ctl

github-actions · 2023-09-21T13:00:19Z

design/dec/el2_dec_tlu_ctl.sv


-assign csr_mhpme5 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-    &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]
+assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

github-actions · 2023-09-21T13:00:19Z

design/dec/el2_dec_tlu_ctl.sv

    &dec_csr_rdaddr_d[0]);

-assign csr_mhpme6 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-    &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

github-actions · 2023-09-21T13:00:19Z

design/dec/el2_dec_tlu_ctl.sv

-assign csr_mhpme6 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
-    &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]
+assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
+    &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
    &!dec_csr_rdaddr_d[0]);

 assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

github-actions · 2023-09-21T13:00:19Z

design/dec/el2_dec_tlu_ctl.sv

    &!dec_csr_rdaddr_d[0]);

 assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
    &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
    &!dec_csr_rdaddr_d[0]);

-assign csr_mitctl0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-    &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);
+assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]

assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]

github-actions · 2023-09-21T13:00:20Z

design/dec/el2_dec_tlu_ctl.sv


-assign csr_mitctl1 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
+assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3]

assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3]

github-actions · 2023-09-21T14:43:52Z

Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2023-09-28T13:58:08Z

design/dec/el2_dec_pmp_ctl.sv

+`include "el2_param.vh"
+ )
+  (
+   input logic clk,
+   input logic free_l2clk,
+   input logic csr_wr_clk,
+   input logic rst_l,
+   input logic        dec_csr_wen_r_mod,  // csr write enable at wb
+   input logic [11:0] dec_csr_wraddr_r,   // write address for csr
+   input logic [31:0] dec_csr_wrdata_r,   // csr write data at wb
+   input logic [11:0] dec_csr_rdaddr_d,   // read address for csr
+
+   input logic csr_pmpcfg,
+   input logic csr_pmpaddr0,
+   input logic csr_pmpaddr16,
+   input logic csr_pmpaddr32,
+   input logic csr_pmpaddr48,
+
+   input logic dec_pause_state, // Paused
+   input logic dec_tlu_pmu_fw_halted, // pmu/fw halted
+   input logic internal_dbg_halt_timers, // debug halted
+
+   output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data
+   output logic        dec_pmp_read_d, // pmp CSR address match
+
+   output el2_pmp_cfg_pkt_t pmp_pmpcfg  [pt.PMP_ENTRIES],
+   output logic [31:0]      pmp_pmpaddr [pt.PMP_ENTRIES],
+
+   input  logic        scan_mode
+   );
+
+   logic wr_pmpcfg_r;
+   logic [3:0] wr_pmpcfg_group;
+
+   logic wr_pmpaddr0_sel;
+   logic wr_pmpaddr16_sel;
+   logic wr_pmpaddr32_sel;
+   logic wr_pmpaddr48_sel;
+   logic wr_pmpaddr_r;
+   logic [1:0] wr_pmpaddr_quarter;
+   logic [5:0] wr_pmpaddr_address;
+
+   logic  [3:0] pmp_quarter_rdaddr;
+   logic [31:0] pmp_pmpcfg_rddata;
+
+   // ----------------------------------------------------------------------
+   // PMPCFGx (RW)
+   // [31:24] : PMP entry (x*4 + 3) configuration
+   // [23:16] : PMP entry (x*4 + 2) configuration
+   // [15:8] : PMP entry (x*4 + 1) configuration
+   //  [7:0] : PMP entry (x*4 + 0) configuration
+
+   localparam PMPCFG       = 12'h3a0;
+
+   assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);
+   assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)
+
+   for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff
+      rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk),
+                          .en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),
+                          .din(dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0] & 8'b10011111),
+                          .dout(pmp_pmpcfg[entry_idx]));
+   end
+
+   // ----------------------------------------------------------------------
+   // PMPADDRx (RW)
+   // [31:0] : PMP entry (x) address selector (word addressing)
+   //
+   // NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping
+   //       to bits 33:32 of the physical address are always set to 0. (WARL)
+
+   localparam  PMPADDR0      = 12'h3b0;
+   localparam PMPADDR16      = 12'h3c0;
+   localparam PMPADDR32      = 12'h3d0;
+   localparam PMPADDR48      = 12'h3e0;
+
+   assign wr_pmpaddr0_sel  = dec_csr_wraddr_r[11:4] ==  PMPADDR0[11:4];
+   assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4];
+   assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4];
+   assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4];
+   assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel);
+
+   assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel;
+   assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel;
+   assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address
+
+   for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff
+      logic pmpaddr_lock;
+      logic pmpaddr_lock_next;
+      assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`include "el2_param.vh"

)

(

input logic clk,

input logic free_l2clk,

input logic csr_wr_clk,

input logic rst_l,

input logic dec_csr_wen_r_mod, // csr write enable at wb

input logic [11:0] dec_csr_wraddr_r, // write address for csr

input logic [31:0] dec_csr_wrdata_r, // csr write data at wb

input logic [11:0] dec_csr_rdaddr_d, // read address for csr

input logic csr_pmpcfg,

input logic csr_pmpaddr0,

input logic csr_pmpaddr16,

input logic csr_pmpaddr32,

input logic csr_pmpaddr48,

input logic dec_pause_state, // Paused

input logic dec_tlu_pmu_fw_halted, // pmu/fw halted

input logic internal_dbg_halt_timers, // debug halted

output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data

output logic dec_pmp_read_d, // pmp CSR address match

output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],

input logic scan_mode

);

logic wr_pmpcfg_r;

logic [3:0] wr_pmpcfg_group;

logic wr_pmpaddr0_sel;

logic wr_pmpaddr16_sel;

logic wr_pmpaddr32_sel;

logic wr_pmpaddr48_sel;

logic wr_pmpaddr_r;

logic [1:0] wr_pmpaddr_quarter;

logic [5:0] wr_pmpaddr_address;

logic [3:0] pmp_quarter_rdaddr;

logic [31:0] pmp_pmpcfg_rddata;

// ----------------------------------------------------------------------

// PMPCFGx (RW)

// [31:24] : PMP entry (x*4 + 3) configuration

// [23:16] : PMP entry (x*4 + 2) configuration

// [15:8] : PMP entry (x*4 + 1) configuration

// [7:0] : PMP entry (x*4 + 0) configuration

localparam PMPCFG = 12'h3a0;

assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);

assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff

rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk),

.en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),

.din(dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0] & 8'b10011111),

.dout(pmp_pmpcfg[entry_idx]));

end

// ----------------------------------------------------------------------

// PMPADDRx (RW)

// [31:0] : PMP entry (x) address selector (word addressing)

//

// NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping

// to bits 33:32 of the physical address are always set to 0. (WARL)

localparam PMPADDR0 = 12'h3b0;

localparam PMPADDR16 = 12'h3c0;

localparam PMPADDR32 = 12'h3d0;

localparam PMPADDR48 = 12'h3e0;

assign wr_pmpaddr0_sel = dec_csr_wraddr_r[11:4] == PMPADDR0[11:4];

assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4];

assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4];

assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4];

assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel);

assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff

logic pmpaddr_lock;

logic pmpaddr_lock_next;

assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)

`include "el2_param.vh"

) (

input logic clk,

input logic free_l2clk,

input logic csr_wr_clk,

input logic rst_l,

input logic dec_csr_wen_r_mod, // csr write enable at wb

input logic [11:0] dec_csr_wraddr_r, // write address for csr

input logic [31:0] dec_csr_wrdata_r, // csr write data at wb

input logic [11:0] dec_csr_rdaddr_d, // read address for csr

input logic csr_pmpcfg,

input logic csr_pmpaddr0,

input logic csr_pmpaddr16,

input logic csr_pmpaddr32,

input logic csr_pmpaddr48,

input logic dec_pause_state, // Paused

input logic dec_tlu_pmu_fw_halted, // pmu/fw halted

input logic internal_dbg_halt_timers, // debug halted

output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data

output logic dec_pmp_read_d, // pmp CSR address match

output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

output logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],

input logic scan_mode

);

logic wr_pmpcfg_r;

logic [3:0] wr_pmpcfg_group;

logic wr_pmpaddr0_sel;

logic wr_pmpaddr16_sel;

logic wr_pmpaddr32_sel;

logic wr_pmpaddr48_sel;

logic wr_pmpaddr_r;

logic [1:0] wr_pmpaddr_quarter;

logic [5:0] wr_pmpaddr_address;

logic [3:0] pmp_quarter_rdaddr;

logic [31:0] pmp_pmpcfg_rddata;

// ----------------------------------------------------------------------

// PMPCFGx (RW)

// [31:24] : PMP entry (x*4 + 3) configuration

// [23:16] : PMP entry (x*4 + 2) configuration

// [15:8] : PMP entry (x*4 + 1) configuration

// [7:0] : PMP entry (x*4 + 0) configuration

localparam PMPCFG = 12'h3a0;

assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);

assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff

rvdffe #(8) pmpcfg_ff (

.*,

.clk (free_l2clk),

.en (wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~pmp_pmpcfg[entry_idx].lock)),

.din (dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0] & 8'b10011111),

.dout(pmp_pmpcfg[entry_idx])

);

end

// ----------------------------------------------------------------------

// PMPADDRx (RW)

// [31:0] : PMP entry (x) address selector (word addressing)

//

// NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping

// to bits 33:32 of the physical address are always set to 0. (WARL)

localparam PMPADDR0 = 12'h3b0;

localparam PMPADDR16 = 12'h3c0;

localparam PMPADDR32 = 12'h3d0;

localparam PMPADDR48 = 12'h3e0;

assign wr_pmpaddr0_sel = dec_csr_wraddr_r[11:4] == PMPADDR0[11:4];

assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4];

assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4];

assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4];

assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel);

assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel;

assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address

for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff

logic pmpaddr_lock;

logic pmpaddr_lock_next;

assign pmpaddr_lock_next = ((entry_idx+1 < pt.PMP_ENTRIES)

github-actions · 2023-09-28T13:58:08Z

design/dec/el2_dec_pmp_ctl.sv

+      assign pmpaddr_lock = pmp_pmpcfg[entry_idx].lock | pmpaddr_lock_next;
+      assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;
+      rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),
+                          .en(wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx)
+                              & (~pmpaddr_lock)),
+                          .din(dec_csr_wrdata_r[29:0]),
+                          .dout(pmp_pmpaddr[entry_idx][29:0]));
+   end
+
+   // CSR read mux
+
+   assign pmp_quarter_rdaddr     = dec_csr_rdaddr_d[3:0];
+   assign pmp_pmpcfg_rddata      = { pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}],
+                                     pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h2}],
+                                     pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h1}],
+                                     pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h0}]
+                                     };
+   assign dec_pmp_read_d         = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48;
+   assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}}    & pmp_pmpcfg_rddata) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign pmpaddr_lock = pmp_pmpcfg[entry_idx].lock | pmpaddr_lock_next;

assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;

rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),

.en(wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx)

& (~pmpaddr_lock)),

.din(dec_csr_wrdata_r[29:0]),

.dout(pmp_pmpaddr[entry_idx][29:0]));

end

// CSR read mux

assign pmp_quarter_rdaddr = dec_csr_rdaddr_d[3:0];

assign pmp_pmpcfg_rddata = { pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h2}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h1}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h0}]

};

assign dec_pmp_read_d = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48;

assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}} & pmp_pmpcfg_rddata) |

assign pmpaddr_lock = pmp_pmpcfg[entry_idx].lock | pmpaddr_lock_next;

assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;

rvdffe #(30) pmpaddr_ff (

.*,

.clk (free_l2clk),

.en (wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx) & (~pmpaddr_lock)),

.din (dec_csr_wrdata_r[29:0]),

.dout(pmp_pmpaddr[entry_idx][29:0])

);

end

// CSR read mux

assign pmp_quarter_rdaddr = dec_csr_rdaddr_d[3:0];

assign pmp_pmpcfg_rddata = {

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h3}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h2}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h1}],

pmp_pmpcfg[{pmp_quarter_rdaddr, 2'h0}]

};

assign dec_pmp_read_d = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48;

assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}} & pmp_pmpcfg_rddata) |

github-actions · 2023-09-28T13:58:08Z

design/dec/el2_dec_tlu_ctl.sv

    &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);

-assign csr_mitb0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]
-    &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);
+assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]

assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]

github-actions · 2023-09-28T13:58:08Z

design/dec/el2_dec_tlu_ctl.sv


-assign csr_mitb1 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
+assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]

assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]

github-actions · 2023-09-28T13:58:08Z

design/dec/el2_dec_tlu_ctl.sv

    &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);

-assign csr_mitcnt0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
-    &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]);
+assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]

assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]

github-actions · 2023-09-28T13:58:11Z

design/dec/el2_dec_tlu_ctl.sv

+    &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]
+    &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]
+    &!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
+    &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);

 assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]

assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]

github-actions · 2023-09-28T13:58:12Z

design/dec/el2_dec_tlu_ctl.sv

+    &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (
+    dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
+    &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
+    &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);

 assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]

assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]

github-actions · 2023-09-28T13:58:12Z

design/el2_pmp.sv

+// limitations under the License.
+
+module el2_pmp
+import el2_pkg::*;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import el2_pkg::*;

import el2_pkg::*;

github-actions · 2023-09-28T13:58:12Z

design/el2_pmp.sv

+  parameter PMP_CHANNELS = 3,
+   // Granularity of NAPOT access,
+   // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
+  parameter PMP_GRANULARITY = 0, // TODO: Move to veer.config
+`include "el2_param.vh"
+)
+   (
+   input  logic              clk,                       // Top level clock
+   input  logic              rst_l,                     // Reset
+   input  logic              scan_mode,                 // Scan mode
+
+   input  el2_pmp_cfg_pkt_t  pmp_pmpcfg    [pt.PMP_ENTRIES],
+   input  logic [31:0]       pmp_pmpaddr   [pt.PMP_ENTRIES],
+
+   input  logic [31:0]       pmp_chan_addr [PMP_CHANNELS],
+   input  el2_pmp_type_pkt_t pmp_chan_type [PMP_CHANNELS],
+   output logic              pmp_chan_err  [PMP_CHANNELS]
+   );
+
+  logic [33:0]                                 csr_pmp_addr_i [pt.PMP_ENTRIES];
+  logic [33:0]                                 pmp_req_addr_i [PMP_CHANNELS];
+
+  logic [33:0]                                 region_start_addr [pt.PMP_ENTRIES];
+  logic [33:PMP_GRANULARITY+2]                 region_addr_mask  [pt.PMP_ENTRIES];
+  logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;
+  logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt;
+  logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq;
+  logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all;
+  logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_basic_perm_check;
+  logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter PMP_CHANNELS = 3,

// Granularity of NAPOT access,

// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.

parameter PMP_GRANULARITY = 0, // TODO: Move to veer.config

`include "el2_param.vh"

)

(

input logic clk, // Top level clock

input logic rst_l, // Reset

input logic scan_mode, // Scan mode

input el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

input logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],

input logic [31:0] pmp_chan_addr [PMP_CHANNELS],

input el2_pmp_type_pkt_t pmp_chan_type [PMP_CHANNELS],

output logic pmp_chan_err [PMP_CHANNELS]

);

logic [33:0] csr_pmp_addr_i [pt.PMP_ENTRIES];

logic [33:0] pmp_req_addr_i [PMP_CHANNELS];

logic [33:0] region_start_addr [pt.PMP_ENTRIES];

logic [33:PMP_GRANULARITY+2] region_addr_mask [pt.PMP_ENTRIES];

logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;

logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt;

logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq;

logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all;

logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_basic_perm_check;

logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;

parameter PMP_CHANNELS = 3,

// Granularity of NAPOT access,

// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.

parameter PMP_GRANULARITY = 0, // TODO: Move to veer.config

`include "el2_param.vh"

) (

input logic clk, // Top level clock

input logic rst_l, // Reset

input logic scan_mode, // Scan mode

input el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],

input logic [31:0] pmp_chan_addr[PMP_CHANNELS],

input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS],

output logic pmp_chan_err [PMP_CHANNELS]

);

logic [ 33:0] csr_pmp_addr_i [pt.PMP_ENTRIES];

logic [ 33:0] pmp_req_addr_i [ PMP_CHANNELS];

logic [ 33:0] region_start_addr [pt.PMP_ENTRIES];

logic [33:PMP_GRANULARITY+2] region_addr_mask [pt.PMP_ENTRIES];

logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;

logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt;

logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq;

logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all;

logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_basic_perm_check;

logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;

github-actions · 2023-09-28T13:58:12Z

design/el2_pmp.sv

+                                              logic             permission_check);
+                          return orig_perm_check(csr_pmp_cfg.lock,
+                                                 permission_check);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic permission_check);

return orig_perm_check(csr_pmp_cfg.lock,

permission_check);

logic permission_check);

return orig_perm_check(csr_pmp_cfg.lock, permission_check);

github-actions · 2023-10-03T14:11:44Z

design/el2_veer.sv

+  el2_pmp_cfg_pkt_t       pmp_pmpcfg  [pt.PMP_ENTRIES];
+  logic [31:0]            pmp_pmpaddr [pt.PMP_ENTRIES];
+  logic [31:0]            pmp_chan_addr [3];
+  el2_pmp_type_pkt_t      pmp_chan_type [3];
+  logic                   pmp_chan_err  [3];


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES];

logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES];

logic [31:0] pmp_chan_addr [3];

el2_pmp_type_pkt_t pmp_chan_type [3];

logic pmp_chan_err [3];

el2_pmp_cfg_pkt_t pmp_pmpcfg[pt.PMP_ENTRIES];

logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES];

logic [31:0] pmp_chan_addr[3];

el2_pmp_type_pkt_t pmp_chan_type[3];

logic pmp_chan_err[3];

github-actions · 2023-10-03T14:11:44Z

design/el2_veer.sv

+  logic                   pmp_chan_err  [3];
+
+  logic [31:1] ifu_pmp_addr;
+  logic        ifu_pmp_error;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic ifu_pmp_error;

logic ifu_pmp_error;

github-actions · 2023-10-03T14:11:44Z

design/el2_veer.sv

+  logic [31:1] ifu_pmp_addr;
+  logic        ifu_pmp_error;
+  logic [31:0] lsu_pmp_addr_start;
+  logic        lsu_pmp_error_start;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic lsu_pmp_error_start;

logic lsu_pmp_error_start;

github-actions · 2023-10-03T14:11:44Z

design/el2_veer.sv

+  logic        lsu_pmp_error_end;
+  logic        lsu_pmp_we;
+  logic        lsu_pmp_re;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic lsu_pmp_error_end;

logic lsu_pmp_we;

logic lsu_pmp_re;

logic lsu_pmp_error_end;

logic lsu_pmp_we;

logic lsu_pmp_re;

github-actions · 2023-10-03T14:11:45Z

design/el2_veer.sv

+  logic        lsu_pmp_error_end;
+  logic        lsu_pmp_we;
+  logic        lsu_pmp_re;
+
   // -----------------------DEBUG  START -------------------------------


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// -----------------------DEBUG START -------------------------------

// -----------------------DEBUG START -------------------------------

github-actions · 2023-10-03T14:11:47Z

design/lsu/el2_lsu_lsc_ctl.sv

      // this signal is used for gpr update
      assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by  }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// this signal is used for gpr update

assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |

// this signal is used for gpr update

assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |

github-actions · 2023-10-03T14:11:47Z

design/lsu/el2_lsu_lsc_ctl.sv

   end else begin: L2U1_Plus1_0 // block: L2U1_Plus1_1
      logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end else begin: L2U1_Plus1_0 // block: L2U1_Plus1_1

logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r;

end else begin : L2U1_Plus1_0 // block: L2U1_Plus1_1

logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r;

github-actions · 2023-10-03T14:11:47Z

design/lsu/el2_lsu_lsc_ctl.sv

      // this result must look at prior stores and merge them in
      assign lsu_result_m[31:0] = ({32{ lsu_pkt_m.unsign & lsu_pkt_m.by  }} & {24'b0,lsu_ld_datafn_m[7:0]}) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// this result must look at prior stores and merge them in

assign lsu_result_m[31:0] = ({32{ lsu_pkt_m.unsign & lsu_pkt_m.by }} & {24'b0,lsu_ld_datafn_m[7:0]}) |

// this result must look at prior stores and merge them in

assign lsu_result_m[31:0] = ({32{ lsu_pkt_m.unsign & lsu_pkt_m.by }} & {24'b0,lsu_ld_datafn_m[7:0]}) |

github-actions · 2023-10-03T14:11:48Z

design/lsu/el2_lsu_lsc_ctl.sv

      // this signal is used for gpr update
      assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by  }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// this signal is used for gpr update

assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |

// this signal is used for gpr update

assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |

github-actions · 2023-10-03T14:11:48Z

design/lsu/el2_lsu_lsc_ctl.sv

+                                                                              ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) |
+                                                                              ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by  }} & {{24{  lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) |
+                                                                              ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{  lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) |
+                                                                              ({32{lsu_pkt_r.word}}                     & lsu_ld_datafn_corr_r[31:0]);
   end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-lint

design/dec/el2_dec.sv|447 col 101| Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
design/dec/el2_dec.sv|448 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
design/dec/el2_dec.sv|449 col 101| Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:53Z

design/lsu/el2_lsu_addrcheck.sv

@@ -124,9 +127,10 @@ import el2_pkg::*;
   assign csr_idx[4:0]       = {start_addr_d[31:28], 1'b1};
   assign is_sideeffects_d = dec_tlu_mrac_ff[csr_idx] & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & lsu_pkt_d.valid & (lsu_pkt_d.store | lsu_pkt_d.load);  //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
   assign is_aligned_d    = (lsu_pkt_d.word & (start_addr_d[1:0] == 2'b0)) |
-                              (lsu_pkt_d.half & (start_addr_d[0] == 1'b0)) |
-                              lsu_pkt_d.by;
+                                                            (lsu_pkt_d.half & (start_addr_d[0] == 1'b0)) |


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:53Z

design/lsu/el2_lsu_addrcheck.sv

@@ -159,13 +164,21 @@ import el2_pkg::*;
                                        (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d))       |   // 0. Addr in dccm/pic region but not in dccm/pic offset
                                        (start_addr_in_dccm_d & end_addr_in_pic_d)                                    |   // 0. DCCM -> PIC cross when DCCM/PIC in same region
                                        (start_addr_in_pic_d  & end_addr_in_dccm_d));                                     // 0. DCCM -> PIC cross when DCCM/PIC in same region
-      assign mpu_access_fault_d      = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok);                              // 3. Address is not in a populated non-dccm region
+    if (pt.PMP_ENTRIES > 0) begin
+      assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                         // X. Address is in blocked region


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 153 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:53Z

design/lsu/el2_lsu_addrcheck.sv

+    if (pt.PMP_ENTRIES > 0) begin
+      assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                         // X. Address is in blocked region
+    end else begin
+      assign mpu_access_fault_d   = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok);                              // 3. Address is not in a populated non-dccm region


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 170 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:53Z

design/lsu/el2_lsu_addrcheck.sv

   end else begin
      assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)                              |   // 0. Addr in dccm region but not in dccm offset
                                        (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)                                  |   // 0. Addr in dccm region but not in dccm offset
                                        (start_addr_in_pic_region_d & ~start_addr_in_pic_d)                                |   // 0. Addr in picm region but not in picm offset
                                        (end_addr_in_pic_region_d & ~end_addr_in_pic_d));                                      // 0. Addr in picm region but not in picm offset
-      assign mpu_access_fault_d      = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region
+    if (pt.PMP_ENTRIES > 0) begin
+      assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                              // X. Address is in blocked region


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:53Z

design/lsu/el2_lsu_addrcheck.sv

+    if (pt.PMP_ENTRIES > 0) begin
+      assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                              // X. Address is in blocked region
+    end else begin
+      assign mpu_access_fault_d   = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 175 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:56Z

design/dec/el2_dec.sv

+    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
+    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
+    input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 148 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:56Z

design/dec/el2_dec.sv

+    input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
+    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
+
+    input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:56Z

design/dec/el2_dec.sv

+    output logic o_cpu_halt_status,  // Halt status of core (pmu/fw)
+    output logic o_cpu_halt_ack,  // Halt request ack
+    output logic o_cpu_run_ack,  // Run request ack
+    output logic o_debug_mode_status,         // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 177 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:56Z

design/dec/el2_dec.sv


+    input logic [70:0] ifu_ic_debug_rd_data,  // diagnostic icache read data
+    input logic ifu_ic_debug_rd_data_valid,  // diagnostic icache read data valid
+    output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:11:56Z

design/dec/el2_dec.sv

+    output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
+    output logic dec_tlu_flush_lower_wb,
+    output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
+    output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]

github-actions · 2023-10-03T14:52:14Z

Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2023-10-04T08:43:03Z

design/lsu/el2_lsu_addrcheck.sv


+  if (pt.PMP_ENTRIES == 0) begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2023-10-04T08:43:03Z

design/lsu/el2_lsu_addrcheck.sv

@@ -159,13 +164,21 @@
                                        (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d))       |   // 0. Addr in dccm/pic region but not in dccm/pic offset
                                        (start_addr_in_dccm_d & end_addr_in_pic_d)                                    |   // 0. DCCM -> PIC cross when DCCM/PIC in same region
                                        (start_addr_in_pic_d  & end_addr_in_dccm_d));                                     // 0. DCCM -> PIC cross when DCCM/PIC in same region
-      assign mpu_access_fault_d      = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok);                              // 3. Address is not in a populated non-dccm region
+    if (pt.PMP_ENTRIES > 0) begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2023-10-04T08:43:03Z

design/lsu/el2_lsu_addrcheck.sv

-      assign mpu_access_fault_d      = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok);                              // 3. Address is not in a populated non-dccm region
+    if (pt.PMP_ENTRIES > 0) begin
+      assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                         // X. Address is in blocked region
+    end else begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2023-10-04T08:43:03Z

design/lsu/el2_lsu_addrcheck.sv

   end else begin
      assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)                              |   // 0. Addr in dccm region but not in dccm offset
                                        (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)                                  |   // 0. Addr in dccm region but not in dccm offset
                                        (start_addr_in_pic_region_d & ~start_addr_in_pic_d)                                |   // 0. Addr in picm region but not in picm offset
                                        (end_addr_in_pic_region_d & ~end_addr_in_pic_d));                                      // 0. Addr in picm region but not in picm offset
-      assign mpu_access_fault_d      = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region
+    if (pt.PMP_ENTRIES > 0) begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2023-10-04T08:43:03Z

design/lsu/el2_lsu_addrcheck.sv

-      assign mpu_access_fault_d      = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region
+    if (pt.PMP_ENTRIES > 0) begin
+      assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                              // X. Address is in blocked region
+    end else begin


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block statements must have a label [Style: generate-statements] [generate-label]

github-actions · 2023-10-04T09:43:34Z

Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2023-10-04T10:22:39Z

Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

…g equations Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48351]

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48351]

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

…error handling Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

…s type enum Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

…set to TOR Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

…from inlining Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

…mparing MCAUSE value Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49661]

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com> Internal-tag: [#49202]

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

robertszczepanski · 2023-10-10T09:04:16Z

I've rebased this branch to remove conflicts after recent main branch merges. Linter suggestions were addressed through adding waiver rules. Formatter suggestions were addressed partially. More formatting and linting improvements will be introduced in a follow up PR.

github-actions · 2023-10-10T10:22:16Z

Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

tmichalak · 2023-10-10T10:26:20Z

LGTM

github-actions bot reviewed Sep 21, 2023

View reviewed changes

koluckirafal force-pushed the pmp branch from 1c629f6 to 858d71a Compare September 28, 2023 13:57

github-actions bot reviewed Sep 28, 2023

View reviewed changes

github-actions bot reviewed Oct 3, 2023

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robertszczepanski force-pushed the pmp branch from 5cbd4e1 to 16ddaab Compare October 4, 2023 08:41

github-actions bot reviewed Oct 4, 2023

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robertszczepanski force-pushed the pmp branch 2 times, most recently from 4b7ee0a to bb6f49a Compare October 4, 2023 08:59

koluckirafal marked this pull request as ready for review October 4, 2023 09:23

robertszczepanski force-pushed the pmp branch from cb01193 to 58e9e8d Compare October 4, 2023 09:27

koluckirafal added 14 commits October 10, 2023 10:07

design/dec: Add PMP CSRs addresses and regenerate CSR address decodin…

e788eeb

…g equations Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48351]

design/dec: Add PMP CSRs implementation

3cbfa75

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48351]

design/dec: Zero unused bits in pmpcfg CSR, fix locking logic

1ab8cb4

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48351]

configs: Fix PMP entries number selection

3d1c8af

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48351]

design/dec: Move PMP CSR contents to the port

3a4bdd2

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design, testbench: Add initial PMP unit implementation

3f2086d

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design/ifu: Pass address and error signals to the ports, add initial …

ee81daa

…error handling Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design/dec: Shorten pmpaddr CSR internally to 30 bits

2fa2555

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design/include: Convert pmpcfg mode field to enum, add memory acces…

dcac646

…s type enum Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design: Adapt PMP to VeeR-EL2 addressing, connect IFU to PMP

f67f69d

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design/lsu: Connect LSU to PMP

c18094d

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design: Fix PMP type channels

3660177

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#48979]

design/dec: Lock PMPADDR(n-1) CSR when PMP entry n is locked and …

f02c737

…set to TOR Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>

design/{lsu/, include/, el2_veer.sv}: Test only valid LSU requests

5224f8c

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>

koluckirafal and others added 14 commits October 10, 2023 10:07

tools, .gitignore: Remove/ignore *.sym files

96294f8

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>

testbench/tests: Add pmp test skeleton

0e40018

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

testbench/tests/pmp: Add fault handling logic

6b06b94

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

testbench/tests/pmp: Add second stack for exception handler

6ea8a0c

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

testbench/tests/pmp: Add load and exec tests

ce8128a

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

testbench/tests/pmp: Add PMP CSR handling

846f454

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

testbench/tests/pmp: Setup PMP in test functions

766bbb8

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

testbench/tests/pmp: Lock entries when setting up, prevent exec test …

8a019b1

…from inlining Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49347]

testbench/tests/pmp: Fix execution test and switch to defines when co…

298013f

…mparing MCAUSE value Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> Internal-tag: [#49661]

.github/workflows: Add PMP program to regression tests

891af0f

Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>

Apply Verible on modified sources

de114b6

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

Add block level tests for PMP

bcbb0bc

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com> Internal-tag: [#49202]

Add simulation generated files to gitignore

203f84e

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com> Internal-tag: [#49202]

Run PMP block level test in CI

afbf4d0

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>

robertszczepanski force-pushed the pmp branch from 58e9e8d to afbf4d0 Compare October 10, 2023 09:01

tmichalak merged commit d0e9a66 into chipsalliance:main Oct 10, 2023
46 checks passed

mczyz-antmicro deleted the pmp branch October 11, 2023 12:03

		@@ -286,6 +286,10 @@ import el2_pkg::*;

		output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet

	output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet
	input logic [15:0] ifu_i0_cinst, // 16b compressed instruction

	assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
	assign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

	assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
	assign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

	assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]
	assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]

	assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
	assign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]


		assign csr_mitctl1 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
		assign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3]

	assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]
	assign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]


		assign csr_mitb1 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]
		assign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]

	assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]
	assign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]

	assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
	assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]

	assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
	assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]

	// -----------------------DEBUG START -------------------------------
	// -----------------------DEBUG START -------------------------------

		// this signal is used for gpr update
		assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) \|

		end else begin: L2U1_Plus1_0 // block: L2U1_Plus1_1
		logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r;

		// this result must look at prior stores and merge them in
		assign lsu_result_m[31:0] = ({32{ lsu_pkt_m.unsign & lsu_pkt_m.by }} & {24'b0,lsu_ld_datafn_m[7:0]}) \|

Physical Memory Protection unit #119

Physical Memory Protection unit #119

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koluckirafal commented Sep 21, 2023 • edited

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koluckirafal commented Sep 21, 2023 •

edited