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Improve riscv-dv tests in CI #122

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mkurc-ant
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This PR fixes several issues with riscv-dv tests in CI:

  • added generation of most of the tests available in riscv-dv
  • the riscv-dv test matrix is built directly from testlist.yaml
  • separated code generation and test running stage from the makefile for riscv-dv
  • fixed issues around code patching for VeeR that mitigates delayed writes not appearing in execution logs

mkurc-ant and others added 7 commits September 28, 2023 15:56
… flow

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Eryk Szpotanski <eszpotanski@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…y scripts

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Links to coverage and verification reports for this PR (#122) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@mkurc-ant mkurc-ant closed this Oct 9, 2023
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Superseeded by #117

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2 participants