Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Symplify variable-length loop syntax in el2_exu_alu_ctl.sv #129

Merged
merged 1 commit into from
Dec 6, 2023
Merged

Symplify variable-length loop syntax in el2_exu_alu_ctl.sv #129

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions design/exu/el2_exu_alu_ctl.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -331,14 +331,14 @@
integer i;
logic found;

always_comb

Check warning on line 334 in design/exu/el2_exu_alu_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/exu/el2_exu_alu_ctl.sv:334:-   always_comb
design/exu/el2_exu_alu_ctl.sv:335:-     begin
design/exu/el2_exu_alu_ctl.sv:336:-        bitmanip_lzd_os[31:0]   =  bitmanip_lzd_in[31:0];
design/exu/el2_exu_alu_ctl.sv:337:-        bitmanip_dw_lzd_enc[5:0]=  6'b0;
design/exu/el2_exu_alu_ctl.sv:338:-        found = 1'b0;
design/exu/el2_exu_alu_ctl.sv:356:+  always_comb begin
design/exu/el2_exu_alu_ctl.sv:357:+    bitmanip_lzd_os[31:0] = bitmanip_lzd_in[31:0];
design/exu/el2_exu_alu_ctl.sv:358:+    bitmanip_dw_lzd_enc[5:0] = 6'b0;
design/exu/el2_exu_alu_ctl.sv:359:+    found = 1'b0;
begin
bitmanip_lzd_os[31:0] = bitmanip_lzd_in[31:0];
bitmanip_dw_lzd_enc[5:0]= 6'b0;
found = 1'b0;

for (int i=0; i<32 && found==0; i++) begin
if (bitmanip_lzd_os[31] == 1'b0) begin
for (int i=0; i<32; i++) begin

Check warning on line 340 in design/exu/el2_exu_alu_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/exu/el2_exu_alu_ctl.sv:340:-        for (int i=0; i<32; i++) begin
design/exu/el2_exu_alu_ctl.sv:341:-          if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
design/exu/el2_exu_alu_ctl.sv:342:-              bitmanip_dw_lzd_enc[5:0]=  bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
design/exu/el2_exu_alu_ctl.sv:343:-              bitmanip_lzd_os[31:0]   =  bitmanip_lzd_os[31:0] << 1;
design/exu/el2_exu_alu_ctl.sv:344:-           end
design/exu/el2_exu_alu_ctl.sv:345:-           else
design/exu/el2_exu_alu_ctl.sv:346:-              found=1'b1;
design/exu/el2_exu_alu_ctl.sv:347:-        end
design/exu/el2_exu_alu_ctl.sv:348:-     end
design/exu/el2_exu_alu_ctl.sv:361:+    for (int i = 0; i < 32; i++) begin
design/exu/el2_exu_alu_ctl.sv:362:+      if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
design/exu/el2_exu_alu_ctl.sv:363:+        bitmanip_dw_lzd_enc[5:0] = bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
design/exu/el2_exu_alu_ctl.sv:364:+        bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1;
design/exu/el2_exu_alu_ctl.sv:365:+      end else found = 1'b1;
design/exu/el2_exu_alu_ctl.sv:366:+    end
design/exu/el2_exu_alu_ctl.sv:367:+  end
if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin
bitmanip_dw_lzd_enc[5:0]= bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;
bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1;
end
Expand Down
Loading