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Add LSU DCCM UVM testbench for Verilator #131

Merged
merged 2 commits into from
Nov 9, 2023
Merged

Add LSU DCCM UVM testbench for Verilator #131

merged 2 commits into from
Nov 9, 2023

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kbieganski
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@kbieganski kbieganski commented Nov 8, 2023 •
edited by kgugala
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Adds a simple DCCM UVM testbench simulated using Verilator.

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Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

testbench/uvm/mem/hdl/mem_sequence.sv|146|
testbench/uvm/mem/hdl/mem_wr_rd_test.sv|16|
testbench/uvm/mem/hdl/mem_wr_rd_test.sv|36|
testbench/uvm/mem/hdl/tbench_top.sv|33|
testbench/uvm/mem/hdl/tbench_top.sv|47|
testbench/uvm/mem/hdl/tbench_top.sv|54|
testbench/uvm/mem/hdl/tbench_top.sv|60|
testbench/uvm/mem/hdl/tbench_top.sv|74|
testbench/uvm/mem/hdl/tbench_top.sv|79|
testbench/uvm/mem/hdl/tbench_top.sv|86|

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@kbieganski kbieganski force-pushed the verilator-uvm-testbench branch 4 times, most recently from 5b1a526 to ef86dd7 Compare November 8, 2023 19:06
@kgugala kgugala marked this pull request as ready for review November 8, 2023 19:18
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Links to coverage and verification reports for this PR (#131) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala changed the title Add LSU DCCM UVM testbench for Verilator [DNM] Add LSU DCCM UVM testbench for Verilator Nov 8, 2023
@kgugala kgugala marked this pull request as draft November 8, 2023 19:40
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github-actions bot commented Nov 8, 2023

Links to coverage and verification reports for this PR (#131) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

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github-actions bot commented Nov 8, 2023

Links to coverage and verification reports for this PR (#131) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala changed the title [DNM] Add LSU DCCM UVM testbench for Verilator Add LSU DCCM UVM testbench for Verilator Nov 9, 2023
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@mkurc-ant @kgugala
Add example UVM testbench for Verilator
f5a4606 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
@kgugala kgugala marked this pull request as ready for review November 9, 2023 05:05
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Links to coverage and verification reports for this PR (#131) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

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github-actions bot commented Nov 9, 2023

Links to coverage and verification reports for this PR (#131) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kbieganski
Add CI workflow for UVM testbench
4a8e19d 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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github-actions bot commented Nov 9, 2023

Links to coverage and verification reports for this PR (#131) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala
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kgugala commented Nov 9, 2023

LGTM!

@kgugala kgugala merged commit 0faacff into chipsalliance:main Nov 9, 2023
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@kgugala kgugala deleted the verilator-uvm-testbench branch November 9, 2023 21:03
@tgorochowik tgorochowik mentioned this pull request Nov 29, 2023
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@kbieganski @kgugala @mkurc-ant