Merge pull request #393 from chipsalliance/dev-msft

Merge dev-msft -> dev-integrate

.github/scripts/gdb_test.sh

@@ -5,6 +5,17 @@
 
 SIM_LOG=`realpath sim.log`
 OPENOCD_LOG=`realpath openocd.log`
+GCC_PREFIX=riscv64-unknown-elf
+
+# Ensure that RISC-V toolchain is installed
+if ! which ${GCC_PREFIX}-gcc >/dev/null; then
+    GCC_PREFIX=riscv32-unknown-elf
+fi
+if ! which ${GCC_PREFIX}-gcc >/dev/null; then
+    echo "RISC-V toolchain not found, please refer to https://github.com/chipsalliance/caliptra-rtl?tab=readme-ov-file#riscv-toolchain-installation for more details."
+    exit 1
+fi
+export GCC_PREFIX
 
 set +e
 

.github/workflows/build-test-verilator.yml

@@ -18,7 +18,7 @@ env:
   SCCACHE_GHA_CACHE_TO: sccache-verilator-10000
   SCCACHE_GHA_CACHE_FROM: sccache-verilator-
   # Change this to a new random value if you suspect the cache is corrupted
-  SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d
+  SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1e
 
 jobs:
   build_tools:
@@ -101,9 +101,8 @@ jobs:
         if: steps.riscv_restore.outputs.cache-hit != 'true'
         run: |
           # Building from source takes around 6.65 GB of disk and download size
-          wget -O toolchain.tar.gz https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv64imc-3.0.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
-          mkdir /opt/riscv
-          tar -xzf toolchain.tar.gz -C /opt/riscv/
+          wget -O toolchain.tar.gz https://github.com/chipsalliance/caliptra-tools/releases/download/gcc-v12.1.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
+          tar -xzf toolchain.tar.gz -C /opt/
 
       - name: Save riscv dir
         uses: actions/cache/save@v3

.github/workflows/interactive-debugging.yml

@@ -22,7 +22,7 @@ jobs:
       SCCACHE_GHA_CACHE_TO: sccache-verilator-10000
       SCCACHE_GHA_CACHE_FROM: sccache-verilator-
       # Change this to a new random value if you suspect the cache is corrupted
-      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d
+      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1e
 
     steps:
       - name: Restore sccache binary
@@ -185,9 +185,8 @@ jobs:
       - name: Install Risc V Toolchain
         run: |
           # Building from source takes around 6.65 GB of disk and download size
-          wget -O toolchain.tar.gz https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv64imc-3.0.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
-          mkdir /opt/riscv
-          tar -xzf toolchain.tar.gz -C /opt/riscv/
+          wget -O toolchain.tar.gz https://github.com/chipsalliance/caliptra-tools/releases/download/gcc-v12.1.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
+          tar -xzf toolchain.tar.gz -C /opt/
 
       - name: Install dependencies
         run: |
@@ -268,9 +267,8 @@ jobs:
       - name: Install Risc V Toolchain
         run: |
           # Building from source takes around 6.65 GB of disk and download size
-          wget -O toolchain.tar.gz https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv64imc-3.0.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
-          mkdir /opt/riscv
-          tar -xzf toolchain.tar.gz -C /opt/riscv/
+          wget -O toolchain.tar.gz https://github.com/chipsalliance/caliptra-tools/releases/download/gcc-v12.1.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
+          tar -xzf toolchain.tar.gz -C /opt/
 
       - name: Download Verilator binaries
         uses: actions/download-artifact@v3

README.md

@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Caliptra Hands-On Guide** #
-_*Last Update: 2023/10/17*_
+_*Last Update: 2024/01/17*_
 
 
 ## **Tools Used** ##
@@ -144,12 +144,12 @@ Verilog file lists are generated via VCS and included in the config directory fo
 ## **Simulation Flow** ##
 
 ### Caliptra Top VCS Steps: ###
-1. Setup tools, add to PATH (ensure riscv64-unknown-elf-gcc is also available)
+1. Setup tools, add to PATH (ensure RISC-V toolchain is also available)
 2. Define all environment variables above
     - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
     - See [Regression Tests](#Regression-Tests) for information about available tests.
 3. Create a run folder for build outputs (and cd to it)
-4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for [iccm_lock](src/integration/test_suites/iccm_lock) test). To do this, copy [iccm_lock.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) to the run directory and rename to `program.hex`. [dccm.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
+4. [OPTIONAL] By default, this run flow will use the RISC-V toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for [iccm_lock](src/integration/test_suites/iccm_lock) test). To do this, copy [iccm_lock.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) to the run directory and rename to `program.hex`. [dccm.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
 5. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}`
     - E.g.: `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex`
     - NOTE: TESTNAME may also be overridden in the makefile command line invocation, e.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=iccm_lock program.hex`
@@ -165,13 +165,13 @@ Verilog file lists are generated via VCS and included in the config directory fo
 8. Simulate project with `caliptra_top_tb` as the top target
 
 ### Caliptra Top Verilator Steps: ###
-1. Setup tools, add to PATH (ensure Verilator, GCC, and riscv64-unknown-elf-gcc are available)
+1. Setup tools, add to PATH (ensure Verilator, GCC, and RISC-V toolchain are available)
 2. Define all environment variables above
     - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
     - See [Regression Tests](#Regression-Tests) for information about available tests.
 3. Create a run folder for build outputs
     - Recommended to place run folder under `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<date>`
-4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
+4. [OPTIONAL] By default, this run flow will use the RISC-V toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
 5. Run Caliptra/tools/scripts/Makefile, which provides steps to run a top-level simulation in Verilator
     - Example command:
         `make -C <path/to/run/folder> -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=${TESTNAME} debug=1 verilator`
@@ -208,7 +208,12 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 - UVM 1.1d installation
 - Mentor Graphics UVM-Framework installation
 
-Steps:<BR>
+**Environment Variables**:<BR>
+`UVM_HOME`: Filesystem path to the parent directory containing SystemVerilog source code for the UVM library of the desired version.
+`UVMF_HOME`: Filesystem path to the parent directory containing source code (uvmf_base_pkg) for the UVM Frameworks library, a tool available from Mentor Graphics for generating baseline UVM projects.
+`QUESTA_MVC_HOME`: Filesystem path to the parent directory containing source code for Mentor Graphics QVIP, the verification library from which AHB/APB UVM agents are pulled in the Caliptra UVM environment.
+
+**Steps:**<BR>
 1. Compile UVM 1.1d library
 1. Compile the AHB/APB QVIP source
 1. Compile the Mentor Graphics UVM-Frameworks base library
@@ -244,7 +249,7 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 - UVM 1.1d installation
 - Mentor Graphics UVM-Framework installation
 
-Steps:<BR>
+**Steps:**<BR>
 1. Compile UVM 1.1d library
 1. Compile the AHB/APB QVIP source
 1. Compile the Mentor Graphics UVM-Frameworks base library

Release_Notes.md

@@ -14,11 +14,33 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2023/11/02*_
+_*Last Update: 2024/01/18*_
 
-## Rev 1p0-rc1 ##
+## Rev 1p0 ##
 
-### Rev 1p0-rc1 release date: 2023/11/03 (1p0 version pending ROM release for official declaration) ###
+### Rev 1p0 release date: 2024/01/18 ###
+- Caliptra Hardware Specification: Markdown conversion
+- Caliptra Integration specification update with synthesis warnings and jtag tck requirement
+- Caliptra README updates to clarify test cases and running with VCS
+- Makefile updates to support DPI compilation in VCS
+- Verification
+  - Adding ECC, DOE, HMAC_DRBG and SHA512_masked formal Assertion IP
+  - JTAG with clock gating test cases
+  - Fixes for UVM caliptra_top test scenarios
+  - Fixes for UVM KeyVault test scenarios
+- Updated synthesis tool from Design Compiler to Fusion Compiler (sanity checks only)
+- RTL
+  - Remove TODO comments on caliptra_top ports
+  - Remove JTAG IDCODE command from RISC-V processor
+
+### Bug Fixes ###
+[MBOX] Fix ICCM Uncorrectable ECC error driving hw_error_non_fatal bit for LSU reads
+
+## Previous Releases ##
+
+### Rev 1p0-rc1 ###
+
+#### Rev 1p0-rc1 release date: 2023/11/03 (1p0 version pending ROM release for official declaration) ###
 - Caliptra IP Specification: see docs/ folder
 - Caliptra Integration Specification: see docs/ folder
 - Caliptra testplan: see docs/ folder
@@ -59,7 +81,7 @@ _*Last Update: 2023/11/02*_
   - Automated GitHub action using OpenOCD for interactive JTAG debugging
   - SHA Formal Verification
 
-### Bug Fixes ###
+#### Bug Fixes ####
 [CLK GATING] Fatal error should wake up clks<br>
 [CLK GATING] JTAG accesses need to wake up clocks<br>
 [DOE] add zeroize to clear all internal regs<br>
@@ -114,8 +136,6 @@ _*Last Update: 2023/11/02*_
 [RST] scan_mode should not corrupt resets<br>
 [TOP] EL2 Mem interface is not instantiated with a modport at all levels
 
-## Previous Releases ##
-
 ### Rev 0p8 ###
 
 #### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. ####