Critical synthesis issues

[syaxiado]

We are running ASIC synthesis of Caliptra IP out of the box with Synopsys DC. There are two critical issue types:

1. Combinatorial timing loops which are showstoppers for an ASIC tapeout.
2. Other serious issues like shorted outputs etc. The attached synthesis check_design report shows all the issues.

Details of Issue #1: Combinatorial timing loops
Information: Timing loop detected. (OPT-150)
u_sb_lsu_ahb_mux/C862/A1 u_sb_lsu_ahb_mux/C862/Z u_sb_lsu_ahb_mux/U10/A1 u_sb_lsu_ahb_mux/U10/Z u_sb_lsu_ahb_mux/U17/A1 u_sb_lsu_ahb_mux/U17/Z u_sb_lsu_ahb_mux/U19/A1 u_sb_lsu_ahb_mux/U19/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U30/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U30/ZN ahb_lite_bus_i/u_ahb_lite_address_decoder/U35/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U35/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U50/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U50/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U62/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U62/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U180/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U180/ZN ahb_lite_bus_i/u_ahb_lite_address_decoder/U181/A2 ahb_lite_bus_i/u_ahb_lite_address_decoder/U181/ZN ahb_lite_bus_i/u_ahb_lite_address_decoder/U193/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U193/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U194/B2 ahb_lite_bus_i/u_ahb_lite_address_decoder/U194/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U195/A2 ahb_lite_bus_i/u_ahb_lite_address_decoder/U195/Z u_sb_lsu_ahb_mux/U114/A1 u_sb_lsu_ahb_mux/U114/Z
Information: Timing loop detected. (OPT-150)
u_sb_lsu_ahb_mux/C856/A2 u_sb_lsu_ahb_mux/C856/Z u_sb_lsu_ahb_mux/U112/I u_sb_lsu_ahb_mux/U112/ZN u_sb_lsu_ahb_mux/U115/A2 u_sb_lsu_ahb_mux/U115/Z u_sb_lsu_ahb_mux/C862/A2 u_sb_lsu_ahb_mux/C862/Z u_sb_lsu_ahb_mux/U10/A1 u_sb_lsu_ahb_mux/U10/Z u_sb_lsu_ahb_mux/U17/A1 u_sb_lsu_ahb_mux/U17/Z u_sb_lsu_ahb_mux/U19/A1 u_sb_lsu_ahb_mux/U19/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U30/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U30/ZN ahb_lite_bus_i/u_ahb_lite_address_decoder/U35/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U35/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U50/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U50/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U62/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U62/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U180/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U180/ZN ahb_lite_bus_i/u_ahb_lite_address_decoder/U181/A2 ahb_lite_bus_i/u_ahb_lite_address_decoder/U181/ZN ahb_lite_bus_i/u_ahb_lite_address_decoder/U193/A1 ahb_lite_bus_i/u_ahb_lite_address_decoder/U193/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U194/B2 ahb_lite_bus_i/u_ahb_lite_address_decoder/U194/Z ahb_lite_bus_i/u_ahb_lite_address_decoder/U195/A2 ahb_lite_bus_i/u_ahb_lite_address_decoder/U195/Z
Warning: Disabling timing arc between pins 'A1' and 'Z' on cell 'u_sb_lsu_ahb_mux/C862'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'A2' and 'Z' on cell 'u_sb_lsu_ahb_mux/C856'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'A1' and 'Z' on cell 'u_sb_lsu_ahb_mux/C877'
to break a timing loop. (OPT-314)

Details of Issue #2 (see attached file): Other serious synthesis issues
caliptra_top.check_design.txt

[Nitsirks]

What version of RTL are you using? The timing loops should have been resolved quite a while ago.

[Nitsirks]

@syaxiado are you still seeing this issue with the latest RTL? We have not seen any timing loops in some time. If this is resolved we can close the issue.

[bharatpillilli]

No activity and others aren't facing the same issue