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Synchronicity of JTAG reset #545

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steven-bellock opened this issue Jul 1, 2024 · 2 comments · Fixed by #546
Closed

Synchronicity of JTAG reset #545

steven-bellock opened this issue Jul 1, 2024 · 2 comments · Fixed by #546
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documentation Improvements or additions to documentation

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@steven-bellock
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The integration specification says

Signal name Width Driver Synchronous (as viewed from Caliptra’s boundary)
jtag_trst_n 1 input Async Deassertion
Assertion Synchronous to tck

However the JTAG reset has asynchronous assertion and (ideally) synchronous deassertion. From 1149.1

If TRST* is included in the TAP, the TAP controller and TMP controller shall be asynchronously reset to the Test-Logic-Reset and Persistence-Off controller states, respectively, when a logic 0 is applied to TRST*...

Note that 1149.1 doesn't say how TRST* should be deasserted but most folks deassert it synchronously to the falling edge of TCK.
@steven-bellock
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@calebofearth you can assign this to me as I already have a pull request for it.

@calebofearth calebofearth added the documentation Improvements or additions to documentation label Jul 1, 2024
steven-bellock added a commit to steven-bellock/caliptra-rtl that referenced this issue Jul 1, 2024
@steven-bellock
Fix up JTAG reset in integration specification
22cfa72 
Fix chipsalliance#545.

Signed-off-by: Steven Bellock <sbellock@nvidia.com>
@steven-bellock steven-bellock mentioned this issue Jul 1, 2024
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calebofearth pushed a commit that referenced this issue Jul 3, 2024
@steven-bellock
Fix up JTAG reset in integration specification (#546)
dea4ee4 
Fix #545.

Signed-off-by: Steven Bellock <sbellock@nvidia.com>
@calebofearth
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Thanks @steven-bellock, I merged this in for the 1.1 release.

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Fix up JTAG reset in integration specification steven-bellock/caliptra-rtl
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@steven-bellock @calebofearth