feat: DW_lbsh wrapper in Chisel

+ write the Chisel wrapper for DW_lbsh;

dwbb/src/interface/DW_lbsh.scala

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2024 Jiuyang Liu <liu@jiuyang.me>
+package org.chipsalliance.dwbb.interface.DW_lbsh
+
+import chisel3._
+import chisel3.experimental.SerializableModuleParameter
+import chisel3.util.log2Ceil
+import upickle.default
+
+object Parameter {
+  implicit def rw: default.ReadWriter[Parameter] =
+    upickle.default.macroRW[Parameter]
+}
+
+case class Parameter(AWidth: Int = 49, SHWidth: Int = 6)
+    extends SerializableModuleParameter {
+  require(AWidth >= 2, "AWidth must be greater than or equal to 2")
+  require(
+    Range.inclusive(0, log2Ceil(AWidth)).contains(SHWidth),
+    s"SHWidth must be between 0 and ${log2Ceil(AWidth)}."
+  )
+}
+
+class Interface(parameter: Parameter) extends Bundle {
+  val A: UInt = Input(UInt(parameter.AWidth.W))
+  val SH: UInt = Input(UInt(parameter.SHWidth.W))
+  val SH_TC: Bool = Input(Bool())
+  val B: UInt = Output(UInt(parameter.AWidth.W))
+}

dwbb/src/wrapper/DW_lbsh.scala

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2024 Jiuyang Liu <liu@jiuyang.me>
+package org.chipsalliance.dwbb.wrapper.DW_lbsh
+
+import chisel3.experimental.IntParam
+import org.chipsalliance.dwbb.interface.DW_lbsh._
+import org.chipsalliance.dwbb.wrapper.WrapperModule
+
+import scala.collection.immutable.SeqMap
+
+class DW_lbsh(parameter: Parameter)
+    extends WrapperModule[Interface, Parameter](
+      new Interface(parameter),
+      parameter,
+      p =>
+        SeqMap(
+          "A_width" -> IntParam(p.AWidth),
+          "SH_width" -> IntParam(p.SHWidth)
+        )
+    )