Improve source locators for intrinsic helpers.

Better to point to where the intrinsic was used, not where the wrapper is defined.
chipsalliance · Apr 25, 2024 · 277bbb6 · 277bbb6
1 parent 08edb71
commit 277bbb6
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Showing 7 changed files with 28 additions and 10 deletions.
diff --git a/src/main/scala/chisel3/util/circt/ClockGate.scala b/src/main/scala/chisel3/util/circt/ClockGate.scala
@@ -3,6 +3,7 @@
 package chisel3.util.circt
 
 import chisel3._
+import chisel3.experimental.SourceInfo
 import chisel3.internal.Builder
 
 object ClockGate {
@@ -16,7 +17,7 @@ object ClockGate {
     * gateClock := ClockGate(clock, enable)
     * }}}
     */
-  def apply(input: Clock, enable: Bool): Clock = {
+  def apply(input: Clock, enable: Bool)(implicit sourceInfo: SourceInfo): Clock = {
     IntrinsicExpr("circt_clock_gate", Clock())(input, enable)
   }
 }
diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala
@@ -3,6 +3,7 @@
 package chisel3.util.circt
 
 import chisel3._
+import chisel3.experimental.SourceInfo
 import chisel3.internal.Builder
 
 object IsX {
@@ -13,7 +14,7 @@ object IsX {
     * b := IsX(a)
     * }}}
     */
-  def apply[T <: Data](gen: T): Bool = {
+  def apply[T <: Data](gen: T)(implicit sourceInfo: SourceInfo): Bool = {
     IntrinsicExpr("circt_isX", Bool())(gen)
   }
 }
diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala
@@ -3,6 +3,7 @@
 package chisel3.util.circt
 
 import chisel3._
+import chisel3.experimental.SourceInfo
 import chisel3.internal.Builder
 
 object PlusArgsTest {
@@ -13,10 +14,10 @@ object PlusArgsTest {
     * b := PlusArgsTest("FOO")
     * }}}
     */
-  def apply(str: String): Bool = {
+  def apply(str: String)(implicit sourceInfo: SourceInfo): Bool = {
     IntrinsicExpr("circt_plusargs_test", Bool(), "FORMAT" -> str)()
   }
 
   @deprecated("use PlusArgsTest(str) instead")
-  def apply[T <: Data](gen: T, str: String): Bool = apply(str)
+  def apply[T <: Data](gen: T, str: String)(implicit sourceInfo: SourceInfo): Bool = apply(str)
 }
diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala
@@ -5,6 +5,7 @@ package chisel3.util.circt
 import scala.language.reflectiveCalls
 
 import chisel3._
+import chisel3.experimental.SourceInfo
 import chisel3.internal.Builder
 
 /** Create an intrinsic which generates a verilog \$value\$plusargs.  This returns a
@@ -21,7 +22,7 @@ object PlusArgsValue {
     * b.value
     * }}}
     */
-  def apply[T <: Data](gen: T, str: String) = {
+  def apply[T <: Data](gen: T, str: String)(implicit sourceInfo: SourceInfo) = {
     val ty = if (gen.isSynthesizable) chiselTypeOf(gen) else gen
     class PlusArgsRetBundle extends Bundle {
       val found = Output(Bool())
@@ -37,7 +38,7 @@ object PlusArgsValue {
     * v := PlusArgsValue(UInt(32.W), "FOO=%d", 42.U)
     * }}}
     */
-  def apply[T <: Data](gen: T, str: String, default: T): T = {
+  def apply[T <: Data](gen: T, str: String, default: T)(implicit sourceInfo: SourceInfo): T = {
     val result = apply(gen, str)
     Mux(result.found, result.result, default)
   }

diff --git a/src/main/scala/chisel3/util/circt/SizeOf.scala b/src/main/scala/chisel3/util/circt/SizeOf.scala
@@ -3,6 +3,8 @@
 package chisel3.util.circt
 
 import chisel3._
+import chisel3.experimental.SourceInfo
+
 object SizeOf {
 
   /** Creates an intrinsic which returns the size of a type.  The returned size
@@ -14,7 +16,7 @@ object SizeOf {
     * a := 1 << (SizeOf(a) - 1)
     * }}}
     */
-  def apply[T <: Data](gen: T): Data = {
+  def apply[T <: Data](gen: T)(implicit sourceInfo: SourceInfo): Data = {
     IntrinsicExpr("circt_sizeof", UInt(32.W))(gen)
   }
 }
diff --git a/src/main/scala/chisel3/util/circt/Synthesis.scala b/src/main/scala/chisel3/util/circt/Synthesis.scala
@@ -3,7 +3,7 @@
 package chisel3.util.circt
 
 import chisel3._
-import chisel3.experimental.requireIsHardware
+import chisel3.experimental.{requireIsHardware, SourceInfo}
 import chisel3.internal.Builder
 
 /** Utility for constructing 2-to-1 MUX cell intrinsic. This intrinsic is lowered into verilog
@@ -22,7 +22,7 @@ object Mux2Cell {
     * val muxOut = Mux2Cell(data_in === 3.U, 3.U(4.W), 0.U(4.W))
     * }}}
     */
-  def apply[T <: Data](cond: UInt, con: T, alt: T): T = {
+  def apply[T <: Data](cond: UInt, con: T, alt: T)(implicit sourceInfo: SourceInfo): T = {
     requireIsHardware(cond, "MUX2 cell selector")
     requireIsHardware(con, "MUX2 cell true value")
     requireIsHardware(alt, "MUX2 cell false value")
@@ -47,7 +47,7 @@ object Mux4Cell {
     * v := Mux4Cell(sel, v3, v2, v1, v0)
     * }}}
     */
-  def apply[T <: Data](sel: UInt, v3: T, v2: T, v1: T, v0: T): T = {
+  def apply[T <: Data](sel: UInt, v3: T, v2: T, v1: T, v0: T)(implicit sourceInfo: SourceInfo): T = {
     requireIsHardware(sel, "4-to-1 mux selector")
     requireIsHardware(v3, "MUX4 cell input value when selector == 3")
     requireIsHardware(v2, "MUX4 cell input value when selector == 2")

diff --git a/src/test/scala/chiselTests/util/circt/IsXSpec.scala b/src/test/scala/chiselTests/util/circt/IsXSpec.scala
@@ -4,6 +4,7 @@ package chiselTests.util.circt
 
 import chisel3._
 import chisel3.stage.ChiselGeneratorAnnotation
+import chisel3.experimental.{SourceInfo, SourceLine}
 import chisel3.testers.BasicTester
 import chisel3.util.circt.IsX
 import circt.stage.ChiselStage
@@ -39,4 +40,15 @@ class IsXSpec extends AnyFlatSpec with Matchers {
       "node _outy_T = intrinsic(circt_isX : UInt<1>, y)"
     )
   }
+  it should "generate source locator for user code" in {
+    val fir = ChiselStage.emitCHIRRTL(new Module {
+      val in = IO(Input(UInt(65.W)))
+      val out = IO(Output(UInt(1.W)))
+      implicit val info = SourceLine("Foo.scala", 1, 2)
+      out := IsX(in)
+    })
+    fir.split('\n').map(_.trim) should contain(
+      "node _out_T = intrinsic(circt_isX : UInt<1>, in) @[Foo.scala 1:2]"
+    )
+  }
 }