Change apply to mem for SRAM shift register implementation

chipsalliance · Jan 19, 2023 · 4f2efb1 · 4f2efb1
1 parent e17d91c
commit 4f2efb1
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
@@ -133,11 +133,11 @@ object ShiftRegister {
     * @param useDualSRAMPort dual port or single port SRAM based implementation
     * @param name name of SyncReadMem object
     */
-  def apply[T <: Data](in: T, n: Int, en: Bool, useDualSRAMPort: Boolean, name: Option[String]): T =
+  def mem[T <: Data](in: T, n: Int, en: Bool, useDualSRAMPort: Boolean, name: Option[String]): T =
     macro SourceInfoTransform.inNEnUseDualSRAMpNameArg
 
   /** @group SourceInfoTransformMacro */
-  def do_apply[T <: Data](
+  def do_mem[T <: Data](
     in:              T,
     n:               Int,
     en:              Bool,
@@ -146,9 +146,9 @@ object ShiftRegister {
   )(
     implicit sourceInfo: SourceInfo,
     compileOptions:      CompileOptions
-  ): T = _apply_impl_sram(in, n, en, useDualSRAMPort, name)
+  ): T = _apply_impl_mem(in, n, en, useDualSRAMPort, name)
 
-  private def _apply_impl_sram[T <: Data](
+  private def _apply_impl_mem[T <: Data](
     in:              T,
     n:               Int,
     en:              Bool = true.B,

diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
@@ -54,7 +54,7 @@ class ShiftTester(n: Int) extends BasicTester {
 class ShiftMemTester(n: Int, dp_mem: Boolean) extends BasicTester {
   val (cntVal, done) = Counter(true.B, n)
   val start = 23.U
-  val sr = ShiftRegister(cntVal + start, n, true.B, dp_mem, Some("simple_sr"))
+  val sr = ShiftRegister.mem(cntVal + start, n, true.B, dp_mem, Some("simple_sr"))
   when(RegNext(done)) {
     assert(sr === start)
     stop()

diff --git a/src/test/scala/chiselTests/util/RegSpec.scala b/src/test/scala/chiselTests/util/RegSpec.scala
@@ -87,7 +87,7 @@ class ShiftRegisterSpec extends AnyFlatSpec with Matchers {
     class MyModule extends Module {
       val in = IO(Input(Bool()))
       val out = IO(Output(Bool()))
-      out := ShiftRegister(in, 2, true.B, false, Some("sr"))
+      out := ShiftRegister.mem(in, 2, true.B, false, Some("sr"))
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
     val reset = """reset .*RegSpec.scala""".r