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fixup! More FIRRTL 3.0.0 updates
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seldridge committed Jun 21, 2023
1 parent 4070d9a commit b0a8977
Showing 1 changed file with 3 additions and 1 deletion.
4 changes: 3 additions & 1 deletion src/test/scala/chiselTests/Mem.scala
Original file line number Diff line number Diff line change
Expand Up @@ -541,7 +541,9 @@ class SRAMSpec extends ChiselFunSpec {
chirrtl should include(s"connect mem_MPORT[$i], mem.writePorts[0].data[$i]")

chirrtl should include(s"when mem.readwritePorts[0].mask[$i]")
chirrtl should include(s"connect mem_out_readwritePorts_0_readData_MPORT[$i], mem.readwritePorts[0].writeData[$i]")
chirrtl should include(
s"connect mem_out_readwritePorts_0_readData_MPORT[$i], mem.readwritePorts[0].writeData[$i]"
)
}
}
describe("Read-only SRAM") {
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