Add requireIsAnnotatable for better errors when annotating literals

core/src/main/scala/chisel3/dontTouch.scala

@@ -2,10 +2,11 @@
 
 package chisel3
 
-import chisel3.experimental.{annotate, requireIsHardware, ChiselAnnotation}
+import chisel3.experimental.{annotate, requireIsAnnotatable, ChiselAnnotation}
 import chisel3.properties.Property
 import chisel3.reflect.DataMirror
 import firrtl.transforms.DontTouchAnnotation
+import chisel3.experimental.requireIsHardware
 
 /** Marks that a signal's leaves are an optimization barrier to Chisel and the
   * FIRRTL compiler. This has the effect of guaranteeing that a signal will not
@@ -34,7 +35,7 @@ object dontTouch {
     * @return Unmodified signal `data`
     */
   def apply[T <: Data](data: T): T = {
-    requireIsHardware(data, "Data marked dontTouch")
+    requireIsAnnotatable(data, "Data marked dontTouch")
     data match {
       case d if DataMirror.hasProbeTypeModifier(d) => ()
       case _:   Property[_] => ()

core/src/main/scala/chisel3/experimental/package.scala

@@ -62,6 +62,20 @@ package object experimental {
     }
   }
 
+  /** Require that a Data can be annotated. It must be non-literal hardware.
+    */
+  object requireIsAnnotatable {
+    def apply(node: Data, msg: String = ""): Unit = {
+      requireIsHardware(node, msg)
+      if (node.isLit) {
+        val prefix = if (msg.nonEmpty) s"$msg " else ""
+        throw ExpectedAnnotatableException(
+          s"$prefix'$node' must not be a literal."
+        )
+      }
+    }
+  }
+
   /** Requires that a node is a chisel type (not hardware, "unbound")
     */
   object requireIsChiselType {

core/src/main/scala/chisel3/package.scala

@@ -398,6 +398,10 @@ package object chisel3 {
     */
   case class ExpectedHardwareException(message: String) extends BindingException(message)
 
+  /** A function expected annotatable hardware
+    */
+  case class ExpectedAnnotatableException(message: String) extends BindingException(message)
+
   /** An aggregate had a mix of specified and unspecified directionality children
     */
   case class MixedDirectionAggregateException(message: String) extends BindingException(message)

src/main/scala/chisel3/util/experimental/decode/decoder.scala

@@ -3,7 +3,7 @@
 package chisel3.util.experimental.decode
 
 import chisel3._
-import chisel3.experimental.{annotate, ChiselAnnotation}
+import chisel3.experimental.{annotate, requireIsAnnotatable, ChiselAnnotation}
 import chisel3.util.{pla, BitPat}
 import chisel3.util.experimental.{getAnnotations, BitSet}
 import firrtl.annotations.Annotation
@@ -30,7 +30,7 @@ object decoder extends LazyLogging {
       val (plaInput, plaOutput) =
         pla(minimizedTable.table.toSeq, BitPat(minimizedTable.default.value.U(minimizedTable.default.getWidth.W)))
 
-      assert(plaOutput.isSynthesizable, s"Using DecodeTableAnnotation on non-hardware value $plaOutput")
+      requireIsAnnotatable(plaOutput, "DecodeTableAnnotation target")
       annotate(new ChiselAnnotation {
         override def toFirrtl: Annotation =
           DecodeTableAnnotation(plaOutput.toTarget, truthTable.toString, minimizedTable.toString)

src/test/scala/chiselTests/DontTouchSpec.scala

@@ -106,6 +106,14 @@ class DontTouchSpec extends ChiselFlatSpec with Utils {
       })
     }
   }
+  it should "not work on literals" in {
+    val e = the[chisel3.ExpectedAnnotatableException] thrownBy {
+      ChiselStage.emitCHIRRTL(new Module {
+        dontTouch(123.U)
+      })
+    }
+    e.getMessage should include("must not be a literal")
+  }
 
   "fields" should "be marked don't touch by default" in {
     val (_, annos) = getFirrtlAndAnnos(new HasDeadCodeLeaves())