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| # FOSS Flows For FPGA (F4PGA) project | ||
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| <p align="center"> | ||
| <a title="Website" href="https://f4pga.org"><img src="https://img.shields.io/website?longCache=true&style=flat-square&label=f4pga.org&up_color=10cfc9&url=https%3A%2F%2Ff4pga.org%2Findex.html&labelColor=fff"></a><!-- | ||
| --> | ||
| <a title="Community" href="https://f4pga.readthedocs.io/en/latest/community.html#communication"><img src="https://img.shields.io/badge/Chat-IRC%20%7C%20Slack-white?longCache=true&style=flat-square&logo=Slack&logoColor=fff"></a><!-- | ||
| <a title="Documentation" href="https://f4pga.readthedocs.io"><img src="https://img.shields.io/website?longCache=true&style=flat-square&label=Documentation&up_color=1226aa&up_message=%E2%9E%9A&url=https%3A%2F%2Ff4pga.readthedocs.io%2Fen%2Flatest%2Findex.html&labelColor=fff"></a><!-- | ||
| --> | ||
| <a title="'Automerge' workflow status" href="https://github.com/chipsalliance/f4pga/actions/workflows/Doc.yml"><img alt="'Automerge' workflow status" src="https://img.shields.io/github/workflow/status/chipsalliance/f4pga/Automerge/main?longCache=true&style=flat-square&label=Tests&logo=Github%20Actions&logoColor=fff"></a><!-- | ||
| <a title="Community" href="https://f4pga.readthedocs.io/en/latest/community.html#communication"><img src="https://img.shields.io/badge/Chat-IRC%20%7C%20Slack-white?longCache=true&style=flat-square&logo=Slack&logoColor=fff"></a><!-- | ||
| --> | ||
| </p> | ||
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| This is the top-level repository for the [F4PGA](https://f4pga.org/) project, which is a Workgroup under the [CHIPS Alliance](https://chipsalliance.org). | ||
| The elements of the project include (but are not limited to): | ||
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| * The F4PGA open source FPGA toolchains for programming FPGAs (formerly known as [SymbiFlow](https://github.com/SymbiFlow)). | ||
| This includes: | ||
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| * [](https://f4pga.readthedocs.io) | ||
| * F4PGA Architecture Definitions [](https://f4pga.readthedocs.io/projects/arch-defs) | ||
| * F4PGA Examples [](https://f4pga-examples.readthedocs.io) | ||
| * [F4PGA Yosys plugins](https://github.com/chipsalliance/yosys-f4pga-plugins) | ||
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| * The FPGA interchange format (an interchange format defined by CHIPS Alliance to enable interoperability between | ||
| different FPGA tools) adopted by the F4PGA toolchain: | ||
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| * [FPGA Interchange schema](https://github.com/chipsalliance/fpga-interchange-schema) | ||
| * [FPGA Interchange Python utilities](https://github.com/chipsalliance/python-fpga-interchange) | ||
| * [FPGA Interchange Test suite](https://github.com/SymbiFlow/fpga-interchange-tests) | ||
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| * The [FPGA tool performance framework](https://github.com/chipsalliance/fpga-tool-perf) framework for benchmarking | ||
| designs against various FPGA tools, and vice versa, over time. | ||
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| * FPGA Database visualisation tools for visual exploration of FPGA bitstream and databases: | ||
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| * [F4PGA bitstream viewer](https://github.com/SymbiFlow/f4pga-bitstream-viewer) | ||
| * [F4PGA database visualizer](https://github.com/chipsalliance/f4pga-database-visualizer) | ||
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| * Other utilities (FPGA assembly format, documentation and other): | ||
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| * [F4PGA Assembly (FASM)](https://github.com/chipsalliance/fasm) | ||
| * [Xilinx bitstream generation library](https://github.com/SymbiFlow/f4pga-xc-fasm) | ||
| * [Verilog-to-routing XML utilities](https://github.com/SymbiFlow/vtr-xml-utils) | ||
| * [SDF format utilities](https://github.com/chipsalliance/python-sdf-timing) | ||
| * [F4PGA tools data manager](https://github.com/SymbiFlow/symbiflow-tools-data-manager) | ||
| * [F4PGA Sphinx Theme](https://github.com/SymbiFlow/sphinx_symbiflow_theme) | ||
| * [F4PGA Sphinx HDL diagrams](https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams) | ||
| * [F4PGA Sphinx Verilog domain](https://github.com/SymbiFlow/sphinx-verilog-domain) | ||
| # FOSS Flows For FPGA (F4PGA) project | ||
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| ## F4PGA Workgroup | ||
| <p align="center"> | ||
| <a title="'Automerge' workflow status" href="https://github.com/chipsalliance/f4pga/actions/workflows/Doc.yml"><img alt="'Automerge' workflow status" src="https://img.shields.io/github/workflow/status/chipsalliance/f4pga/Automerge/main?longCache=true&style=flat-square&label=Tests&logo=Github%20Actions&logoColor=fff"></a><!-- | ||
| --> | ||
| </p> | ||
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| The F4PGA Workgroup consists of members from different backgrounds, including FPGA vendors | ||
| ([Xilinx](https://www.xilinx.com/) and [QuickLogic](https://www.quicklogic.com/)), | ||
| industrial users | ||
| ([Google](https://www.google.com/), [Antmicro](https://antmicro.com/)) | ||
| and academia | ||
| ([University of Toronto](https://www.utoronto.ca/)), | ||
| This is the top-level repository for the [F4PGA](https://f4pga.org/) project, which is a Workgroup under the [CHIPS Alliance](https://chipsalliance.org); consisting of members from different backgrounds, including FPGA vendors, industrial users and academia (see [Documentation > Community](https://f4pga.readthedocs.io/en/latest/community.html)); | ||
| who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the | ||
| adoption of FPGAs in existing and new use cases, and eliminate barriers of entry. | ||
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| * [Documentation > Getting started](https://f4pga.readthedocs.io) (for everyone) | ||
| * [F4PGA Examples](https://f4pga-examples.readthedocs.io) (for users) | ||
| * [F4PGA Architecture Definitions](https://f4pga.readthedocs.io/projects/arch-defs) (for developers) |
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| # f4pga python package | ||
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| This is the current in-development FPGA-oriented build system that's provided with f4pga. | ||
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| This package aims to provide a unified front-end for executing _verilog-to-bitstream_ and | ||
| other flows for various FPGA platforms. It's meant as a future replacement of | ||
| `symbiflow_*` shell scripts. | ||
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| It contains _EDA_ tool wrappers that provide meta-data about the tools, utilities | ||
| related to tracking files and inspection of data used within the flows, scripts used by | ||
| tools within flows, a dependency resolution algorithm and flow templates for various devices. | ||
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| The basic usage requires creation of a `flow.json` file describing the FPGA-oriented project. | ||
| You can take | ||
| [one from the f4pga-examples repository](https://github.com/chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json) | ||
| as a reference. Alternatively there's a way to configure a flow with command-line parameters only. | ||
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| Once you have your flow created, run | ||
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| ``` | ||
| f4pga build -f flow.json | ||
| ``` | ||
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| to build a default target. | ||
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| To learn more about the package and its usage, visit | ||
| [related section in the docs](https://f4pga.readthedocs.io/en/latest/f4pga/index.html). | ||
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| -------------------------------------------------- | ||
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| ## Package capability status: | ||
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| * Architecture support: | ||
| * Xilinx XC7 (**available** in main branch) | ||
| * Synthesis tool: yosys | ||
| * PnR tool: VPR | ||
| * bitstream generation: yes (xcfasm) | ||
| * used in f4pga-examples: | ||
| [yes](https://github.com/chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json) | ||
| * Quicklogic EOS-S3 (yosys+VPR flow) (**WIP**, see | ||
| [#577](https://github.com/chipsalliance/f4pga/pull/577)) | ||
| * Synthesis tool: yosys | ||
| * PnR tool: VPR | ||
| * bitstream generation: yes (qlfasm) | ||
| * analysis: ? | ||
| * used in f4pga-examples: no | ||
| * Lattice ICE40 (yosys+nextpnr flow) (**WIP**, see | ||
| [#585](https://github.com/chipsalliance/f4pga/pull/585)) | ||
| * Synthesis tool: yosys | ||
| * PnR tool: nextpnr | ||
| * bitstream generation: yes (icepack) | ||
| * used in f4pga-examples: no | ||
| * Quicklogic k4n8 (Unverified, not officially supported. Might work after some tinkering.) | ||
| * Synthesis tool: yosys | ||
| * PnR tool: VPR | ||
| * bitstream generation: yes (qlf_fasm) | ||
| * used in f4pga-examples: no | ||
| * Incremental builds support | ||
| * Support for multiple configurations for a single project | ||
| * Can be used as a python interface to _F4PGA_, however there's no official _API_ at the moment. | ||
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| ## Contributing | ||
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| We welcome contributions from all people as long as they don't include any discriminatory, hateful | ||
| language, don't force users to use proprietary technologies and are related to the F4PGA project. | ||
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| We will prioritize contributions which serve to improve support for platforms that are | ||
| officially supported by _f4pga_. UX-related contributions are welcome as well. | ||
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| ## Reporting bugs | ||
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| If you find a bug and want other to take a look, please open an issue, attach a log and a minimal | ||
| example for reproducing the bug. Use `-vv` (maximum verbosity level) option when running `f4pga` | ||
| if possible. | ||
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| Please, remember to specify the version of architecture definitions you are using (this applies only to VPR-based flows). | ||
| If you used a pre-built packages, please provide a hash that identifies the package and name | ||
| of the platform in question (_XC7_/_EOS-S3_). | ||
| The hash is the last alphanumeric component before the `.tar.gz` suffix of the archive with | ||
| prebuilt packages. Use your local installation to look-up the hash. Links to packages in | ||
| [the documention](https://f4pga-examples.readthedocs.io/en/latest/getting.html) get automatically | ||
| updated to point to the latest packages. | ||
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| If you built the architecture definitions yourself, please specify the hash of the commit you've | ||
| used. | ||
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| If you don't specify the version of architecture definitions, we might be unable to reproduce the | ||
| bug. | ||
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| ## Licensing | ||
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| f4pga is a Free Open-Source Software licensed under Apache 2.0 license. | ||
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| .. _Glossary: | ||
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| Glossary | ||
| ######## | ||
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