f4pga: yosys TCL wrappers moved from f4pga-arch-defs

f4pga/__init__.py

@@ -75,6 +75,8 @@
 ROOT = Path(__file__).resolve().parent
 
 FPGA_FAM = environ.get('FPGA_FAM', 'xc7')
+if FPGA_FAM not in ['xc7', 'eos-s3', 'qlf_k4n8']:
+    raise(Exception(f"Unsupported FPGA_FAM <{FPGA_FAM}>!"))
 
 bin_dir_path = str(Path(sys_argv[0]).resolve().parent.parent)
 share_dir_path = \

f4pga/common_modules/synth.py

@@ -22,6 +22,7 @@
 
 from f4pga.common import decompose_depname, get_verbosity_level, sub as common_sub
 from f4pga.module import Module, ModuleContext
+from f4pga.wrappers.tcl import get_script_path as get_tcl_wrapper_path
 
 
 def yosys_setup_tcl_env(tcl_env_def):
@@ -100,16 +101,19 @@ def execute(self, ctx: ModuleContext):
         tcl_env = yosys_setup_tcl_env(ctx.values.yosys_tcl_env) \
             if ctx.values.yosys_tcl_env else {}
         split_inouts = Path(tcl_env["UTILS_PATH"]) / 'split_inouts.py'
-        synth_tcl = Path(ctx.values.tcl_scripts) / 'synth.tcl'
-        conv_tcl = Path(ctx.values.tcl_scripts) / 'conv.tcl'
 
         if get_verbosity_level() >= 2:
             yield f'Synthesizing sources: {ctx.takes.sources}...'
         else:
             yield f'Synthesizing sources...'
 
-        yosys_synth(str(synth_tcl), tcl_env, ctx.takes.sources,
-                    ctx.values.read_verilog_args, ctx.outputs.synth_log)
+        yosys_synth(
+            str(get_tcl_wrapper_path('synth')),
+            tcl_env,
+            ctx.takes.sources,
+            ctx.values.read_verilog_args,
+            ctx.outputs.synth_log
+        )
 
         yield f'Splitting in/outs...'
         common_sub('python3', str(split_inouts), '-i', ctx.outputs.json, '-o',
@@ -120,7 +124,11 @@ def execute(self, ctx: ModuleContext):
                 wfptr.write('')
 
         yield f'Converting...'
-        yosys_conv(str(conv_tcl), tcl_env, ctx.outputs.synth_json)
+        yosys_conv(
+            str(get_tcl_wrapper_path('conv')),
+            tcl_env,
+            ctx.outputs.synth_json
+        )
 
     def __init__(self, params):
         self.name = 'synthesize'

f4pga/setup.py

@@ -83,7 +83,8 @@ def get_requirements(file: Path) -> List[str]:
     packages=[
         "f4pga",
         "f4pga.common_modules",
-        "f4pga.wrappers.sh"
+        "f4pga.wrappers.sh",
+        "f4pga.wrappers.tcl"
     ],
     package_dir={"f4pga": "."},
     package_data={
@@ -93,6 +94,12 @@ def get_requirements(file: Path) -> List[str]:
         'f4pga.wrappers.sh': [
             'xc7/*.f4pga.sh',
             'quicklogic/*.f4pga.sh'
+        ],
+        'f4pga.wrappers.tcl': [
+            'xc7/*.f4pga.tcl',
+            'eos-s3/*.f4pga.tcl',
+            'qlf_k4n8/*.f4pga.tcl',
+            'ice40/*.f4pga.tcl',
         ]
     },
     classifiers=[],

f4pga/wrappers/sh/__init__.py

@@ -25,16 +25,15 @@
 from shutil import which
 from subprocess import check_call
 
+from f4pga import FPGA_FAM
 
 python3 = which('python3')
 
 f4pga_environ = environ.copy()
 
 ROOT = Path(__file__).resolve().parent
 
-FPGA_FAM = f4pga_environ.get('FPGA_FAM', 'xc7')
-isQuickLogic = FPGA_FAM == 'eos-s3'
-
+isQuickLogic = FPGA_FAM != 'xc7'
 SH_SUBDIR = 'quicklogic' if isQuickLogic else FPGA_FAM
 
 F4PGA_INSTALL_DIR = f4pga_environ.get('F4PGA_INSTALL_DIR')
@@ -433,6 +432,7 @@ def generate_bitstream():
 done
 if [ -z $DEVICE ]; then echo "Please provide device name"; exit 1; fi
 if [ -z $FASM ]; then echo "Please provide an input FASM file name"; exit 1; fi
+if [ ! -f "$FASM" ]; then echo "File <$FASM> does not exist!"; exit 1; fi
 if [ -z $BIT ]; then echo "Please provide an output bistream file name"; exit 1; fi
 """ + f"""
 if [[ "$DEVICE" =~ ^(qlf_k4n8.*)$ ]]; then

f4pga/wrappers/sh/quicklogic/synth.f4pga.sh

@@ -123,8 +123,8 @@ PINMAPCSV="pinmap_${PART}.csv"
 
 export TECHMAP_PATH="${F4PGA_SHARE_DIR}/techmaps/${FAMILY}"
 
-SYNTH_TCL_PATH="${F4PGA_SHARE_DIR}/scripts/${FAMILY}/synth.tcl"
-CONV_TCL_PATH="${F4PGA_SHARE_DIR}/scripts/${FAMILY}/conv.tcl"
+SYNTH_TCL_PATH="$(python3 -m f4pga.wrappers.tcl synth "${FAMILY}")"
+CONV_TCL_PATH="$(python3 -m f4pga.wrappers.tcl conv "${FAMILY}")"
 
 export USE_ROI="FALSE"
 export OUT_JSON=$TOP.json

f4pga/wrappers/sh/xc7/synth.f4pga.sh

@@ -21,7 +21,7 @@ set -e
 export TECHMAP_PATH="${F4PGA_SHARE_DIR}"/techmaps/xc7_vpr/techmap
 
 export UTILS_PATH="${F4PGA_SHARE_DIR}"/scripts
-SYNTH_TCL_PATH=${UTILS_PATH}/xc7/synth.tcl
+SYNTH_TCL_PATH="$(python3 -m f4pga.wrappers.tcl synth)"
 
 VERILOG_FILES=()
 XDC_FILES=()
@@ -140,4 +140,4 @@ else
 fi
 
 python3 ${UTILS_PATH}/split_inouts.py -i ${OUT_JSON} -o ${SYNTH_JSON}
-yosys -p "read_json $SYNTH_JSON; tcl ${UTILS_PATH}/xc7/conv.tcl"
+yosys -p "read_json $SYNTH_JSON; tcl $(python3 -m f4pga.wrappers.tcl conv)"

f4pga/wrappers/tcl/__init__.py

@@ -0,0 +1,59 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020-2022 F4PGA Authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# TCL scripts moved from f4pga-arch-defs
+
+from pathlib import Path
+from f4pga import FPGA_FAM
+
+ROOT = Path(__file__).resolve().parent
+
+ARCHS = {
+    'xc7': [
+        'artix7',
+        'artix7_100t',
+        'artix7_200t',
+        'zynq7',
+        'zynq7_z020',
+        'spartan7'
+    ],
+    'eos-s3': [
+        'ql-s3',
+        'pp3'
+    ]
+}
+
+
+def get_script_path(arg, arch = None):
+    if arch is None:
+        arch = FPGA_FAM
+    for key, val in ARCHS.items():
+        if arch in val:
+            arch = key
+            break
+    if arch not in [
+        'xc7',
+        'eos-s3',
+        'qlf_k4n8',
+        'ice40'
+    ]:
+        raise(Exception(f"Unsupported arch <{arch}>!"))
+    if arg not in ['synth', 'conv']:
+        raise Exception(f'Unknown tcl wrapper <{arg}>!')
+    return ROOT / arch / f'{arg}.f4pga.tcl'

f4pga/wrappers/tcl/__main__.py

@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020-2022 F4PGA Authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+from sys import argv as sys_argv
+
+from f4pga.wrappers.tcl import get_script_path
+
+
+if __name__ == '__main__':
+    print(get_script_path(sys_argv[1], sys_argv[2]) if len(sys_argv)>2 else get_script_path(sys_argv[1]))

f4pga/wrappers/tcl/eos-s3/conv.f4pga.tcl

@@ -0,0 +1,11 @@
+yosys -import
+
+# Clean
+opt_clean
+
+# Write EBLIF
+write_blif -attr -cname -param \
+    -true VCC VCC \
+    -false GND GND \
+    -undef VCC VCC \
+    $::env(OUT_EBLIF)