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f4pga: add f4pga utils command support and add auxDir builtin variable #635

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f4pga: add f4pga utils command support and add auxDir builtin variable #635

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103ba42
mv f4pga/utils f4pga/aux/utils
umarcor Sep 6, 2022
b8ac98c
f4pga: add f4pga utils command support and add auxDir builtin variable
lpawelcz Aug 12, 2022
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0 f4pga/utils/eblif.py → f4pga/aux/utils/eblif.py
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0 f4pga/utils/pcf.py → f4pga/aux/utils/pcf.py
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0 .../utils/quicklogic/convert_compile_opts.py → .../utils/quicklogic/convert_compile_opts.py
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0 f4pga/utils/quicklogic/create_lib.py → f4pga/aux/utils/quicklogic/create_lib.py
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0 f4pga/utils/quicklogic/pinmap_parse.py → f4pga/aux/utils/quicklogic/pinmap_parse.py
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6 changes: 3 additions & 3 deletions f4pga/utils/quicklogic/pp3/arch_import.py → ...a/aux/utils/quicklogic/pp3/arch_import.py
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import lxml.etree as ET

from f4pga.utils.quicklogic.pp3.data_structs import ConnectionType, Loc
from f4pga.aux.utils.quicklogic.pp3.data_structs import ConnectionType, Loc

from f4pga.utils.quicklogic.pp3.tile_import import make_top_level_pb_type
from f4pga.utils.quicklogic.pp3.tile_import import make_top_level_tile
from f4pga.aux.utils.quicklogic.pp3.tile_import import make_top_level_pb_type
from f4pga.aux.utils.quicklogic.pp3.tile_import import make_top_level_tile

# =============================================================================

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4 changes: 2 additions & 2 deletions f4pga/utils/quicklogic/pp3/connections.py → ...a/aux/utils/quicklogic/pp3/connections.py
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import sys

print("PYTHONPATH: {}".format(sys.path))
from f4pga.utils.quicklogic.pp3.data_structs import (
from f4pga.aux.utils.quicklogic.pp3.data_structs import (
SwitchboxPinType,
Loc,
OPPOSITE_DIRECTION,
Expand All @@ -35,7 +35,7 @@
ConnectionType,
PinDirection,
)
from f4pga.utils.quicklogic.pp3.utils import find_cell_in_tile
from f4pga.aux.utils.quicklogic.pp3.utils import find_cell_in_tile

# =============================================================================

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8 changes: 4 additions & 4 deletions ...ils/quicklogic/pp3/create_default_fasm.py → ...ils/quicklogic/pp3/create_default_fasm.py
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import lxml.etree as ET

from f4pga.utils.quicklogic.pp3.data_structs import PinDirection, SwitchboxPinType
from f4pga.utils.quicklogic.pp3.data_import import import_data
from f4pga.utils.quicklogic.pp3.utils import yield_muxes
from f4pga.utils.quicklogic.pp3.switchbox_model import SwitchboxModel
from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection, SwitchboxPinType
from f4pga.aux.utils.quicklogic.pp3.data_import import import_data
from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes
from f4pga.aux.utils.quicklogic.pp3.switchbox_model import SwitchboxModel

# =============================================================================
duplicate = {}
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4 changes: 2 additions & 2 deletions f4pga/utils/quicklogic/pp3/create_ioplace.py → ...ux/utils/quicklogic/pp3/create_ioplace.py
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import re
from collections import defaultdict

import f4pga.utils.vpr_io_place as vpr_io_place
from f4pga.utils.pcf import parse_simple_pcf
import f4pga.aux.utils.vpr_io_place as vpr_io_place
from f4pga.aux.utils.pcf import parse_simple_pcf

# =============================================================================

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2 changes: 1 addition & 1 deletion ...uicklogic/pp3/create_place_constraints.py → ...uicklogic/pp3/create_place_constraints.py
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import sys
import csv

import f4pga.utils.eblif as eblif
import f4pga.aux.utils.eblif as eblif

# =============================================================================

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8 changes: 4 additions & 4 deletions f4pga/utils/quicklogic/pp3/data_import.py → ...a/aux/utils/quicklogic/pp3/data_import.py
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import lxml.etree as ET

from f4pga.utils.quicklogic.pp3.data_structs import (
from f4pga.aux.utils.quicklogic.pp3.data_structs import (
Pin,
PinDirection,
Quadrant,
Expand All @@ -49,9 +49,9 @@
PackagePin,
OPPOSITE_DIRECTION,
)
from f4pga.utils.quicklogic.pp3.utils import yield_muxes, get_loc_of_cell, find_cell_in_tile, natural_keys
from f4pga.utils.quicklogic.pp3.connections import build_connections, check_connections
from f4pga.utils.quicklogic.pp3.connections import hop_to_str, get_name_and_hop, is_regular_hop_wire
from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes, get_loc_of_cell, find_cell_in_tile, natural_keys
from f4pga.aux.utils.quicklogic.pp3.connections import build_connections, check_connections
from f4pga.aux.utils.quicklogic.pp3.connections import hop_to_str, get_name_and_hop, is_regular_hop_wire

# =============================================================================

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0 f4pga/utils/quicklogic/pp3/data_structs.py → .../aux/utils/quicklogic/pp3/data_structs.py
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4 changes: 2 additions & 2 deletions ...ils/quicklogic/pp3/eos-s3/iomux_config.py → ...ils/quicklogic/pp3/eos-s3/iomux_config.py
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import re
import sys

from f4pga.utils.pcf import parse_simple_pcf
from f4pga.utils.eblif import parse_blif
from f4pga.aux.utils.pcf import parse_simple_pcf
from f4pga.aux.utils.eblif import parse_blif

# =============================================================================

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8 changes: 4 additions & 4 deletions f4pga/utils/quicklogic/pp3/fasm2bels.py → f4pga/aux/utils/quicklogic/pp3/fasm2bels.py
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from collections import defaultdict, namedtuple
import fasm

from f4pga.utils.quicklogic.pp3.connections import get_name_and_hop
from f4pga.aux.utils.quicklogic.pp3.connections import get_name_and_hop

from pathlib import Path
from f4pga.utils.quicklogic.pp3.data_structs import Loc, SwitchboxPinLoc, PinDirection, ConnectionType
from f4pga.utils.quicklogic.pp3.utils import get_quadrant_for_loc
from f4pga.utils.quicklogic.pp3.verilogmodule import VModule
from f4pga.aux.utils.quicklogic.pp3.data_structs import Loc, SwitchboxPinLoc, PinDirection, ConnectionType
from f4pga.aux.utils.quicklogic.pp3.utils import get_quadrant_for_loc
from f4pga.aux.utils.quicklogic.pp3.verilogmodule import VModule

from quicklogic_fasm.qlfasm import load_quicklogic_database, get_db_dir
from quicklogic_fasm.qlfasm import QL732BAssembler
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12 changes: 6 additions & 6 deletions ...ls/quicklogic/pp3/prepare_vpr_database.py → ...ls/quicklogic/pp3/prepare_vpr_database.py
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from sdf_timing import sdfparse
from sdf_timing.utils import get_scale_seconds

from f4pga.utils.quicklogic.pp3.data_structs import (
from f4pga.aux.utils.quicklogic.pp3.data_structs import (
Pin,
PinDirection,
Cell,
Expand All @@ -43,12 +43,12 @@
VprSegment,
Quadrant,
)
from f4pga.utils.quicklogic.pp3.utils import get_loc_of_cell, find_cell_in_tile
from f4pga.utils.quicklogic.pp3.utils import get_pin_name
from f4pga.aux.utils.quicklogic.pp3.utils import get_loc_of_cell, find_cell_in_tile
from f4pga.aux.utils.quicklogic.pp3.utils import get_pin_name

from f4pga.utils.quicklogic.pp3.timing import compute_switchbox_timing_model
from f4pga.utils.quicklogic.pp3.timing import populate_switchbox_timing, copy_switchbox_timing
from f4pga.utils.quicklogic.pp3.timing import add_vpr_switches_for_cell
from f4pga.aux.utils.quicklogic.pp3.timing import compute_switchbox_timing_model
from f4pga.aux.utils.quicklogic.pp3.timing import populate_switchbox_timing, copy_switchbox_timing
from f4pga.aux.utils.quicklogic.pp3.timing import add_vpr_switches_for_cell

# =============================================================================

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8 changes: 4 additions & 4 deletions f4pga/utils/quicklogic/pp3/routing_import.py → ...ux/utils/quicklogic/pp3/routing_import.py
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import lib.rr_graph_xml.graph2 as rr_xml
from lib import progressbar_utils

from f4pga.utils.quicklogic.pp3.data_structs import Loc, ConnectionType
from f4pga.utils.quicklogic.pp3.utils import fixup_pin_name
from f4pga.aux.utils.quicklogic.pp3.data_structs import Loc, ConnectionType
from f4pga.aux.utils.quicklogic.pp3.utils import fixup_pin_name

from f4pga.utils.quicklogic.pp3.rr_utils import add_node, add_track, add_edge, connect
from f4pga.utils.quicklogic.pp3.switchbox_model import SwitchboxModel, QmuxSwitchboxModel
from f4pga.aux.utils.quicklogic.pp3.rr_utils import add_node, add_track, add_edge, connect
from f4pga.aux.utils.quicklogic.pp3.switchbox_model import SwitchboxModel, QmuxSwitchboxModel

# =============================================================================

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4 changes: 1 addition & 3 deletions f4pga/utils/quicklogic/pp3/rr_utils.py → f4pga/aux/utils/quicklogic/pp3/rr_utils.py
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# SPDX-License-Identifier: Apache-2.0


from f4pga.utils.quicklogic.pp3.data_structs import Loc
from f4pga.aux.utils.quicklogic.pp3.data_structs import Loc

from lib.rr_graph import tracks
import lib.rr_graph.graph2 as rr

# =============================================================================


def add_track(graph, track, segment_id, node_timing=None):
"""
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8 changes: 3 additions & 5 deletions ...a/utils/quicklogic/pp3/switchbox_model.py → ...x/utils/quicklogic/pp3/switchbox_model.py
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from collections import defaultdict

from f4pga.utils.quicklogic.pp3.data_structs import PinDirection, ConnectionType
from f4pga.utils.quicklogic.pp3.utils import yield_muxes
from f4pga.utils.quicklogic.pp3.rr_utils import add_node, connect

# =============================================================================
from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection, ConnectionType
from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes
from f4pga.aux.utils.quicklogic.pp3.rr_utils import add_node, connect


class SwitchboxModel(object):
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6 changes: 2 additions & 4 deletions f4pga/utils/quicklogic/pp3/tile_import.py → ...a/aux/utils/quicklogic/pp3/tile_import.py
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import lxml.etree as ET

from f4pga.utils.quicklogic.pp3.data_structs import PinDirection
from f4pga.utils.quicklogic.pp3.utils import fixup_pin_name, get_pin_name

# =============================================================================
from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection
from f4pga.aux.utils.quicklogic.pp3.utils import fixup_pin_name, get_pin_name


def add_ports(xml_parent, pins, buses=True):
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6 changes: 2 additions & 4 deletions f4pga/utils/quicklogic/pp3/timing.py → f4pga/aux/utils/quicklogic/pp3/timing.py
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from copy import deepcopy
from collections import defaultdict, namedtuple

from f4pga.utils.quicklogic.pp3.data_structs import VprSwitch, MuxEdgeTiming, DriverTiming, SinkTiming
from f4pga.utils.quicklogic.pp3.utils import yield_muxes, add_named_item

# =============================================================================
from f4pga.aux.utils.quicklogic.pp3.data_structs import VprSwitch, MuxEdgeTiming, DriverTiming, SinkTiming
from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes, add_named_item


def linear_regression(xs, ys):
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0 f4pga/utils/quicklogic/pp3/utils.py → f4pga/aux/utils/quicklogic/pp3/utils.py
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4 changes: 3 additions & 1 deletion f4pga/utils/quicklogic/pp3/verilogmodule.py → ...aux/utils/quicklogic/pp3/verilogmodule.py
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# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0


import re
from collections import namedtuple, defaultdict

from f4pga.utils.quicklogic.pp3.data_structs import PinDirection
from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection

Element = namedtuple("Element", "loc type name ios")
Wire = namedtuple("Wire", "srcloc name inverted")
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8 changes: 4 additions & 4 deletions ...a/utils/quicklogic/pp3/vis_switchboxes.py → ...x/utils/quicklogic/pp3/vis_switchboxes.py
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# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0


import argparse

import lxml.etree as ET

from f4pga.utils.quicklogic.pp3.data_structs import SwitchboxPinType
from f4pga.utils.quicklogic.pp3.data_import import import_data

# =============================================================================
from f4pga.aux.utils.quicklogic.pp3.data_structs import SwitchboxPinType
from f4pga.aux.utils.quicklogic.pp3.data_import import import_data


def fixup_pin_name(name):
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4 changes: 2 additions & 2 deletions ...ils/quicklogic/process_sdc_constraints.py → ...ils/quicklogic/process_sdc_constraints.py
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import re
import csv

from f4pga.utils.pcf import parse_simple_pcf, PcfIoConstraint
from f4pga.utils.eblif import parse_blif
from f4pga.aux.utils.pcf import parse_simple_pcf, PcfIoConstraint
from f4pga.aux.utils.eblif import parse_blif


RE_INDICES = re.compile(r"(?P<name>\S+)\[(?P<i0>[0-9]+):(?P<i1>[0-9]+)\]")
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8 changes: 4 additions & 4 deletions ...ils/quicklogic/qlf_k4n8/create_ioplace.py → ...ils/quicklogic/qlf_k4n8/create_ioplace.py
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import re
from collections import defaultdict

import f4pga.utils.vpr_io_place as vpr_io_place
from f4pga.utils.quicklogic.pinmap_parse import read_pinmapfile_data
from f4pga.utils.quicklogic.pinmap_parse import vec_to_scalar
import f4pga.aux.utils.vpr_io_place as vpr_io_place
from f4pga.aux.utils.quicklogic.pinmap_parse import read_pinmapfile_data
from f4pga.aux.utils.quicklogic.pinmap_parse import vec_to_scalar

from f4pga.utils.pcf import parse_simple_pcf
from f4pga.aux.utils.pcf import parse_simple_pcf

# =============================================================================

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0 f4pga/utils/quicklogic/repacker/README.md → ...a/aux/utils/quicklogic/repacker/README.md
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0 ...ils/quicklogic/repacker/arch_xml_utils.py → ...ils/quicklogic/repacker/arch_xml_utils.py
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0 ...a/utils/quicklogic/repacker/block_path.py → ...x/utils/quicklogic/repacker/block_path.py
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0 ...tils/quicklogic/repacker/eblif_netlist.py → ...tils/quicklogic/repacker/eblif_netlist.py
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0 ...s/quicklogic/repacker/netlist_cleaning.py → ...s/quicklogic/repacker/netlist_cleaning.py
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2 changes: 1 addition & 1 deletion ...ils/quicklogic/repacker/packed_netlist.py → ...ils/quicklogic/repacker/packed_netlist.py
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import re
import lxml.etree as ET

from f4pga.utils.quicklogic.repacker.block_path import PathNode
from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode

# =============================================================================

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12 changes: 6 additions & 6 deletions .../utils/quicklogic/repacker/pb_rr_graph.py → .../utils/quicklogic/repacker/pb_rr_graph.py
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from enum import Enum

from f4pga.utils.quicklogic.repacker.block_path import PathNode
from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode

from f4pga.utils.quicklogic.repacker.pb_type import PortType
from f4pga.aux.utils.quicklogic.repacker.pb_type import PortType

from f4pga.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype
from f4pga.utils.quicklogic.repacker.arch_xml_utils import get_parent_pb
from f4pga.utils.quicklogic.repacker.arch_xml_utils import yield_pb_children
from f4pga.utils.quicklogic.repacker.arch_xml_utils import yield_pins
from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype
from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import get_parent_pb
from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import yield_pb_children
from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import yield_pins

# =============================================================================

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4 changes: 2 additions & 2 deletions ...uicklogic/repacker/pb_rr_graph_netlist.py → ...uicklogic/repacker/pb_rr_graph_netlist.py
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routing information.
"""

from f4pga.utils.quicklogic.repacker.block_path import PathNode
from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode

import f4pga.utils.quicklogic.repacker.packed_netlist as packed_netlist
import f4pga.aux.utils.quicklogic.repacker.packed_netlist as packed_netlist

# =============================================================================

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2 changes: 1 addition & 1 deletion ...quicklogic/repacker/pb_rr_graph_router.py → ...quicklogic/repacker/pb_rr_graph_router.py
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import logging

from f4pga.utils.quicklogic.repacker.pb_rr_graph import NodeType
from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph import NodeType

# =============================================================================

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4 changes: 2 additions & 2 deletions f4pga/utils/quicklogic/repacker/pb_type.py → .../aux/utils/quicklogic/repacker/pb_type.py
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from copy import deepcopy
from enum import Enum

from f4pga.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype
from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype

from f4pga.utils.quicklogic.repacker.block_path import PathNode
from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode

# =============================================================================

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24 changes: 11 additions & 13 deletions f4pga/utils/quicklogic/repacker/repack.py → ...a/aux/utils/quicklogic/repacker/repack.py
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Expand Up @@ -41,23 +41,21 @@
import json
import lxml.etree as ET

from f4pga.utils.quicklogic.repacker.block_path import PathNode
from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode

from f4pga.utils.quicklogic.repacker.eblif_netlist import Eblif, Cell
import f4pga.utils.quicklogic.repacker.netlist_cleaning as netlist_cleaning
from f4pga.aux.utils.quicklogic.repacker.eblif_netlist import Eblif, Cell
import f4pga.aux.utils.quicklogic.repacker.netlist_cleaning as netlist_cleaning

import f4pga.utils.quicklogic.repacker.packed_netlist as pn
from f4pga.utils.quicklogic.repacker.packed_netlist import PackedNetlist
from f4pga.utils.quicklogic.repacker.pb_rr_graph import Graph, NodeType
from f4pga.utils.quicklogic.repacker.pb_rr_graph_router import Router
import f4pga.aux.utils.quicklogic.repacker.packed_netlist as pn
from f4pga.aux.utils.quicklogic.repacker.packed_netlist import PackedNetlist
from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph import Graph, NodeType
from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph_router import Router

from f4pga.utils.quicklogic.repacker.pb_rr_graph_netlist import load_clb_nets_into_pb_graph
from f4pga.utils.quicklogic.repacker.pb_rr_graph_netlist import build_packed_netlist_from_pb_graph
from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph_netlist import load_clb_nets_into_pb_graph
from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph_netlist import build_packed_netlist_from_pb_graph

from f4pga.utils.quicklogic.repacker.pb_type import PbType, Model, PortType
from f4pga.utils.pcf import parse_simple_pcf

# =============================================================================
from f4pga.aux.utils.quicklogic.repacker.pb_type import PbType, Model, PortType
from f4pga.aux.utils.pcf import parse_simple_pcf


class RepackingRule:
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2 changes: 1 addition & 1 deletion f4pga/utils/vpr_io_place.py → f4pga/aux/utils/vpr_io_place.py
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Expand Up @@ -23,7 +23,7 @@
import re
import lxml.etree as ET

from f4pga.utils.eblif import parse_blif
from f4pga.aux.utils.eblif import parse_blif

IoConstraint = namedtuple("IoConstraint", "name x y z comment")

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4 changes: 2 additions & 2 deletions f4pga/utils/xc7/create_ioplace.py → f4pga/aux/utils/xc7/create_ioplace.py
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from sys import stdout, stderr, exit as sys_exit
from json import dump as json_dump, load as json_load

from f4pga.utils.vpr_io_place import IoPlace
from f4pga.utils.pcf import parse_simple_pcf
from f4pga.aux.utils.vpr_io_place import IoPlace
from f4pga.aux.utils.pcf import parse_simple_pcf


def p_main(blif, map, net, pcf=None, output=stdout, iostandard_defs_file=None, iostandard="LVCMOS33", drive=12):
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