Emit space after 'if' for all Verilog conditional synchronous assignm…

…ents (#2091)
chipsalliance · Feb 25, 2021 · 89e9ab0 · 89e9ab0
1 parent edb91f7
commit 89e9ab0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
@@ -756,7 +756,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       val lines = noResetAlwaysBlocks.getOrElseUpdate(clk, ArrayBuffer[Seq[Any]]())
       if (weq(en, one)) lines += Seq(e, " <= ", value, ";")
       else {
-        lines += Seq("if(", en, ") begin")
+        lines += Seq("if (", en, ") begin")
         lines += Seq(tab, e, " <= ", value, ";", info)
         lines += Seq("end")
       }