Emit space after 'if' for all Verilog conditional synchronous assignments

[albert-magyar]

Type of improvement: Verilog readability
API impact: none
Backend code-generation impact: whitespace-only change
Desired merge strategy: squash
Release notes:
Whitespace is used more consistently in emitted Verilog conditional blocks.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you update the FIRRTL spec to include every new feature/behavior?
• [] Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you state the API impact?
• Did you specify the code generation impact?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels?
• Did you mark the proper milestone (1.2.x, 1.3.0, 1.4.0) ?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
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[seldridge]

lgtm

Thanks @albert-magyar!