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exception vectors go to .data #129
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This issue should be gone for the bare program mode. |
We do core level verification , but the core includes internal memories, memory mapped interrupt controller we need to verify. L/S unit needs stimuli with mixed targets ... |
we also have a minimum MMU/MPU logic which defines memory characteristics based on address - |
Does the core support virtual address translation? |
It doesn’t, but we have plans for future versions. We’re also planning multithreaded cores with amo instructions for synchronization.
From: taoliug <notifications@github.com>
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Subject: Re: [google/riscv-dv] exception vectors go to .data (#129)
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Does the core support virtual address translation?
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Right now the the program generate many data pages with label : data_page_{idx}. The default setting is 40 4KB data pages. One easy way to achieve your goal is to link these pages to the various regions in your memory map, so that existing load/store instruction can access different regions naturally. Another way to do it to name the data pages in a more meaningful way. Like |
Don’t they all belong to the same .data section? As far as I know linker operates with sections, not labels. If you prepend your data pages with “.section dataN”, these pages can be relocated by linker to any address independently –
Interesting useful feature could be to use the generator to select physical addresses for these pages …
( I think, there is special .section format to define start address, like .org XXXX command)
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Subject: Re: [google/riscv-dv] exception vectors go to .data (#129)
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Right now the the program generate many data pages with label : data_page_{idx}. The default setting is 40 4KB data pages. One easy way to achieve your goal is to link these pages to the various regions in your memory map, so that existing load/store instruction can access different regions naturally. Another way to do it to name the data pages in a more meaningful way. Like
{
region_0_name : 4KB
region_1_name: 16KB
region_2_name: 512B
....
}
In your link script, you can link each region to corresponding address. This will complicate the page table setup though.
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Let me give a try for the custom region setting. Use .org might be a better idea as it reduce the complexity of the link script. |
Link script can use something like {data* } => .data to put all dataN sections to one output .data section to emulate current behavior ( I don’t remember exact syntax).
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Subject: Re: [google/riscv-dv] exception vectors go to .data (#129)
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Let me give a try for the custom region setting. Use .org might be a better idea as it reduce the complexity of the link script.
{
data_section_0_name ,0x0001_0000, 4KB, instruction
data_section_1_name ,0x0002_0000, 16KB, data
data_section_2_name ,0x0003_F000, 16KB, data
....
}
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The main complexity comes from setting up page tables for these scattered data pages. Especially if we want to inject error in the page table entry and do error recovery. I need to think about a clean way to do it. Right now the assumption is that all pages are equal size and continuously allocated in memory space. I think it makes sense to allow user customize the page location/size/access_type. |
I agree it’s not simple .. we have 4 data pointers in our tests – one for internal data memory, another for external “normal” , one – for I/O type external and one for our internal I/O. Our test gen mixes L/S instructions with all these pointers in the instruction streams . Limitation is that we had to reserve 4 GPRs for these pointers and accesses can go to 4KB windows only.
To check address aliasing effects it may be not sufficient, especially if the CPU includes data cache . ( we don’t have DC, though)
Other L/Ss with random addresses can be created with a sequence, setting up data pointer, but then it’s too deterministic, one more possibility is to get data pointers from memory tables – to check L/L or L/S dependencies
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Subject: Re: [google/riscv-dv] exception vectors go to .data (#129)
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The main complexity comes from setting up page tables for these scattered data pages. Especially if we want to inject error in the page table entry and do error recovery. I need to think about a clean way to do it. Right now the assumption is that all pages are equal size and continuously allocated in memory space. I think it makes sense to allow user customize the page location/size/access_type.
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to my original complain - when you place code(exception handlers in this case) to data sections it confuses some tools you can have sections in the source file as layered cake: at output all .text will be collected together and and all .data together too, forming one .text and one .data |
yes, this issue should have been fixed by this change. .text |
why it is section text.init and not just .text? .macro init |
I think this is inherited from riscv-tests, it's used by link script to link this section to beginning of the program. Maybe for your use case, you want it to be .text so that you can have your own init section? |
Yes, I had to change manually this one to .text ..
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Subject: Re: [google/riscv-dv] exception vectors go to .data (#129)
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I think this is inherited from riscv-tests, it's used by link script to link this section to beginning of the program. Maybe for your use case, you want it to be .text so that you can have your known init section?
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With above changes, now each memory region as it's own section, You can link them to match the memory map. Memory region can be configured in the config class: [Nr] Name Type Address Offset |
any idea, why am I getting region sections with zero data? |
Because there are three data patterns for the data section typedef enum bit [1:0] { |
Is the data pattern randomly selected? |
One more thing can you add _finish: label to the _exit, something like this: _exit: |
one more idea: |
Hi All |
Can you extend riscv_asm_program_gen::gen_program_end to add this? I don't want to add TB specific logic in the upstream code. |
I am closing this issue for now as I believe the original issue is solved. Please file a different issue for other feature requests. Thanks. |
This is already implemented:
|
@eroom1966 , _finish label is used by our RTL verification environment . |
seems that exception code goes to .data section:
.word 0x3a7db1e6, 0xd412cc8d, 0x735721c1, 0x881570db, 0x2f9b3971, 0x825922ad, 0xb5f05d35, 0xc1ae9a38
.align 4;
.align 5
_user_stack_start:
.rept 4999
.4byte 0x0
.endr
_user_stack_end:
.4byte 0x0
_kernel_start: .align 12
smode_program: slt t2, t0, t1
c.beqz a4, smode_program_stack_p
smode_program_stack_p:addi sp, sp, -52
sll s3, s2, s7
sw ra, 4(sp)
sw t0, 8(sp)
sw s9, 12(sp)
mulhsu s5, a2, ra
sw a2, 16(sp)
sw t3, 20(sp)
sw t1, 24(sp)
c.andi a3, 16
diag.exe: file format elf32-littleriscv
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00011a38 00000000 00000000 00001000 21
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .text.init 000000da 00011a38 00011a38 00012a38 20
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .data 00039e22 00012000 00012000 00013000 212
CONTENTS, ALLOC, LOAD, DATA
3 .tohost 00000048 0004be40 0004be40 0004ce40 26
CONTENTS, ALLOC, LOAD, DATA
It should be nice to get things in correct sections to be able to move them around with linker:
.text, .data. .stack .init, .handlers
Also what is the mechanism to define multiple data sections and their addresses? ( we have several memory regions with different characteristics - internal data, instructions, I/O, external normal memories and I/O regions,)
We would like to have several text and data sections be placed in these "RTL/TB defined" addresses.
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