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Re-organize data page generation #135

Merged

taoliug merged 1 commit into master from data

Sep 8, 2019

Contributor

taoliug commented Sep 8, 2019

Allow user to specify the range of each memory region
Assign a separate section for each memory region so that it can be linked to match system memory map.
Refactor load/store/amo test

update #129


          Re-organize data page generation

873180c

taoliug merged commit 7a1a94a into master

taoliug deleted the data branch

September 11, 2019 21:20

udinator pushed a commit to udinator/ibex that referenced this pull request


          Update google_riscv-dv to chipsalliance/riscv-dv@c98d89c

af31802

Update code from upstream repository https://github.com/google/riscv-
dv to revision c98d89cdff7b56d9911904e05e6b46e005233280

* Interrupt test integration (Udi)
* Update README for illegal/hint instruction (chipsalliance/riscv-dv#155)
  (taoliug)
* Refactor illegal/hint instruction generation (chipsalliance/riscv-dv#154)
  (taoliug)
* Skip x0 in GPR save/restore (chipsalliance/riscv-dv#153) (taoliug)
* Move user_define.h to the beginning of the program (google/riscv-
  dv#151) (taoliug)
* Add user_define.h (chipsalliance/riscv-dv#149) (taoliug)
* Move instr_bin to a separate section (chipsalliance/riscv-dv#148) (taoliug)
* Remove temp files (chipsalliance/riscv-dv#145) (taoliug)
* Move dv_defines.svh outside the package (chipsalliance/riscv-dv#144)
  (taoliug)
* Fix typo (chipsalliance/riscv-dv#141) (taoliug)
* Refactored loop instruction stream, reduce global reserved registers
  (chipsalliance/riscv-dv#139) (taoliug)
* Remove obsolete sample program (chipsalliance/riscv-dv#138) (taoliug)
* Update readme (chipsalliance/riscv-dv#137) (taoliug)
* Skip kernel instruction/data pages when not needed (google/riscv-
  dv#136) (taoliug)
* Re-organize data page generation (chipsalliance/riscv-dv#135) (taoliug)
* Re-organize text and data section (chipsalliance/riscv-dv#134) (taoliug)
* Refine the bare program mode (chipsalliance/riscv-dv#133) (taoliug)
* Add a bare program mode (chipsalliance/riscv-dv#130) (taoliug)
* Allow running riscv-dv from other directories (chipsalliance/riscv-dv#128)
  (taoliug)
* Fix trace compare issue (chipsalliance/riscv-dv#123) (taoliug)
* Optimize for constraint solving performance (chipsalliance/riscv-dv#122)
  (taoliug)
* Avoid ISS simulation timeout (chipsalliance/riscv-dv#121) (taoliug)
* Optimize irun randomization performance (chipsalliance/riscv-dv#120)
  (taoliug)
* fix ius compile/simulation warnings (Tao Liu)
* Fix ius compilation failure (Tao Liu)
* Fix chipsalliance/riscv-dv#109 ius constraint solver failure (Tao Liu)
* Add ebreak sequence generation and cmdline options (Udi)
* Added dret instruction to random generation (Udi)
* Tighten up regex in spike log tracer. (Dave Estes)
* Fix generation of debug handshake (Udi)
* Fix wfi generation, add indent to core_initialization handshake
  (Udi)

udinator mentioned this pull request

Update google_riscv-dv to google/riscv-dv@c98d89c lowRISC/ibex#312

Merged

udinator pushed a commit to lowRISC/ibex that referenced this pull request


          Update google_riscv-dv to chipsalliance/riscv-dv@c98d89c (#312)

3fcf5a6

Update code from upstream repository https://github.com/google/riscv-
dv to revision c98d89cdff7b56d9911904e05e6b46e005233280

* Interrupt test integration (Udi)
* Update README for illegal/hint instruction (chipsalliance/riscv-dv#155)
  (taoliug)
* Refactor illegal/hint instruction generation (chipsalliance/riscv-dv#154)
  (taoliug)
* Skip x0 in GPR save/restore (chipsalliance/riscv-dv#153) (taoliug)
* Move user_define.h to the beginning of the program (google/riscv-
  dv#151) (taoliug)
* Add user_define.h (chipsalliance/riscv-dv#149) (taoliug)
* Move instr_bin to a separate section (chipsalliance/riscv-dv#148) (taoliug)
* Remove temp files (chipsalliance/riscv-dv#145) (taoliug)
* Move dv_defines.svh outside the package (chipsalliance/riscv-dv#144)
  (taoliug)
* Fix typo (chipsalliance/riscv-dv#141) (taoliug)
* Refactored loop instruction stream, reduce global reserved registers
  (chipsalliance/riscv-dv#139) (taoliug)
* Remove obsolete sample program (chipsalliance/riscv-dv#138) (taoliug)
* Update readme (chipsalliance/riscv-dv#137) (taoliug)
* Skip kernel instruction/data pages when not needed (google/riscv-
  dv#136) (taoliug)
* Re-organize data page generation (chipsalliance/riscv-dv#135) (taoliug)
* Re-organize text and data section (chipsalliance/riscv-dv#134) (taoliug)
* Refine the bare program mode (chipsalliance/riscv-dv#133) (taoliug)
* Add a bare program mode (chipsalliance/riscv-dv#130) (taoliug)
* Allow running riscv-dv from other directories (chipsalliance/riscv-dv#128)
  (taoliug)
* Fix trace compare issue (chipsalliance/riscv-dv#123) (taoliug)
* Optimize for constraint solving performance (chipsalliance/riscv-dv#122)
  (taoliug)
* Avoid ISS simulation timeout (chipsalliance/riscv-dv#121) (taoliug)
* Optimize irun randomization performance (chipsalliance/riscv-dv#120)
  (taoliug)
* fix ius compile/simulation warnings (Tao Liu)
* Fix ius compilation failure (Tao Liu)
* Fix chipsalliance/riscv-dv#109 ius constraint solver failure (Tao Liu)
* Add ebreak sequence generation and cmdline options (Udi)
* Added dret instruction to random generation (Udi)
* Tighten up regex in spike log tracer. (Dave Estes)
* Fix generation of debug handshake (Udi)
* Fix wfi generation, add indent to core_initialization handshake
  (Udi)

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