Move HasDebugModule out of TileContextType

src/main/scala/devices/debug/Periphery.scala

@@ -14,6 +14,7 @@ import freechips.rocketchip.jtag._
 import freechips.rocketchip.util._
 import freechips.rocketchip.prci.{ClockSinkParameters, ClockSinkNode}
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts.{NullIntSyncSource}
 
 /** Protocols used for communicating with external debugging tools */
 sealed trait DebugExportProtocol
@@ -71,16 +72,16 @@ class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bund
   */
 
 trait HasPeripheryDebug { this: BaseSubsystem =>
-  private val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere)
+  private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere)
 
-  val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
-  val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
+  lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
+  lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
   val debugTLDomainOpt = p(DebugModuleKey).map { _ =>
     val domain = ClockSinkNode(Seq(ClockSinkParameters()))
     domain := tlbus.fixedClockNode
     domain
   }
-  val debugOpt = p(DebugModuleKey).map { params =>
+  lazy val debugOpt = p(DebugModuleKey).map { params =>
     val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
 
     tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus) := _ }
@@ -98,6 +99,8 @@ trait HasPeripheryDebug { this: BaseSubsystem =>
     tlDM
   }
 
+  lazy val debugNode = debugOpt.map(_.intnode).getOrElse(NullIntSyncSource())
+
   val psd = InModuleBody {
     val psd = IO(new PSDIO)
     psd

src/main/scala/groundtest/GroundTestSubsystem.scala

@@ -8,6 +8,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, LazyModule}
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
 import freechips.rocketchip.subsystem.{BaseSubsystem, BaseSubsystemModuleImp, HasTiles, CanHaveMasterAXI4MemPort}
 import freechips.rocketchip.tilelink.{TLRAM, TLFragmenter}
+import freechips.rocketchip.interrupts.{NullIntSyncSource}
 
 class GroundTestSubsystem(implicit p: Parameters)
   extends BaseSubsystem
@@ -25,6 +26,9 @@ class GroundTestSubsystem(implicit p: Parameters)
 
   val tileStatusNodes = tiles.collect { case t: GroundTestTile => t.statusNode.makeSink() }
 
+  // no debug module
+  val debugNode = NullIntSyncSource()
+
   override lazy val module = new GroundTestSubsystemModuleImp(this)
 }
 

src/main/scala/interrupts/NullIntSource.scala

@@ -18,8 +18,14 @@ class NullIntSource(num: Int = 1, ports: Int = 1, sources: Int = 1)(implicit p:
 }
 
 object NullIntSource {
-  def apply(num: Int = 1, ports: Int = 1, sources: Int = 1)(implicit p: Parameters): IntNode = {
+  def apply(num: Int = 1, ports: Int = 1, sources: Int = 1)(implicit p: Parameters): IntOutwardNode = {
     val null_int_source = LazyModule(new NullIntSource(num, ports, sources))
     null_int_source.intnode
   }
 }
+
+object NullIntSyncSource {
+  def apply(num: Int = 1, ports: Int = 1, sources: Int = 1)(implicit p: Parameters): IntSyncOutwardNode = {
+    IntSyncCrossingSource() := NullIntSource(num, ports, sources)
+  }
+}

src/main/scala/interrupts/package.scala

@@ -12,6 +12,10 @@ package object interrupts
   type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, IntEdge, Vec[Bool]]
   type IntNode = SimpleNodeHandle[IntSourcePortParameters, IntSinkPortParameters, IntEdge, Vec[Bool]]
 
+  type IntSyncInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, IntEdge, SyncInterrupts]
+  type IntSyncOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, IntEdge, SyncInterrupts]
+  type IntSyncNode = SimpleNodeHandle[IntSourcePortParameters, IntSinkPortParameters, IntEdge, SyncInterrupts]
+
   implicit class IntClockDomainCrossing(private val x: HasClockDomainCrossing) extends AnyVal {
     def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardClockCrossingHelper(valName.name, x, n)
     def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardClockCrossingHelper(valName.name, x, n)

src/main/scala/subsystem/HasTiles.scala

@@ -5,7 +5,6 @@ package freechips.rocketchip.subsystem
 import chisel3._
 import chisel3.dontTouch
 import org.chipsalliance.cde.config.{Field, Parameters}
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 import freechips.rocketchip.devices.tilelink.{BasicBusBlocker, BasicBusBlockerParams, CLINTConsts, PLICKey, CanHavePeripheryPLIC, CanHavePeripheryCLINT}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
@@ -102,7 +101,6 @@ case class TileSlavePortParams(
 trait HasTileInterruptSources
   extends CanHavePeripheryPLIC
   with CanHavePeripheryCLINT
-  with HasPeripheryDebug
   with InstantiatesTiles
 { this: BaseSubsystem => // TODO ideally this bound would be softened to LazyModule
   /** meipNode is used to create a single bit subsystem input in Configs without a PLIC */
@@ -230,7 +228,9 @@ trait DefaultTileContextType
   with HasTileInterruptSources
   with HasTileNotificationSinks
   with HasTileInputConstants
-{ this: BaseSubsystem => } // TODO: ideally this bound would be softened to LazyModule
+{ this: BaseSubsystem =>
+  val debugNode: IntSyncOutwardNode
+} // TODO: ideally this bound would be softened to LazyModule
 
 /** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources.
   *
@@ -291,10 +291,7 @@ trait CanAttachTile {
     //       we stub out missing interrupts with constant sources here.
 
     // 1. Debug interrupt is definitely asynchronous in all cases.
-    domain.tile.intInwardNode :=
-      context.debugOpt
-        .map { domain { IntSyncAsyncCrossingSink(3) } := _.intnode }
-        .getOrElse { NullIntSource() }
+    domain.tile.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNode
 
     // 2. The CLINT and PLIC output interrupts are synchronous to the TileLink bus clock,
     //    so might need to be synchronized depending on the Tile's crossing type.

src/main/scala/subsystem/RocketSubsystem.scala

@@ -6,6 +6,7 @@ import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing}
 import freechips.rocketchip.tile._
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 
 case class RocketCrossingParams(
   crossingType: ClockCrossingType = SynchronousCrossing(),
@@ -29,7 +30,7 @@ trait HasRocketTiles extends HasTiles { this: BaseSubsystem =>
   }).toList
 }
 
-class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem with HasRocketTiles {
+class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem with HasRocketTiles with HasPeripheryDebug {
   override lazy val module = new RocketSubsystemModuleImp(this)
 }