Skip to content

Commit

Permalink
feat: port Chisel2 to Chisel3 devices/
Browse files Browse the repository at this point in the history
  • Loading branch information
@SingularityKChen @sequencer
SingularityKChen authored and sequencer committed Mar 1, 2023
1 parent 84533ae commit 1ff0db3
Show file tree
Hide file tree
Showing 9 changed files with 144 additions and 139 deletions.
2 changes: 1 addition & 1 deletion src/main/scala/devices/tilelink/ClockBlocker.scala
View file
Expand Up @@ -2,7 +2,7 @@

package freechips.rocketchip.devices.tilelink

import Chisel._
import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
Expand Down
12 changes: 6 additions & 6 deletions src/main/scala/devices/tilelink/Deadlock.scala
View file
Expand Up @@ -2,7 +2,7 @@

package freechips.rocketchip.devices.tilelink

import Chisel._
import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._

Expand All @@ -17,10 +17,10 @@ class TLDeadlock(params: DevNullParams, beatBytes: Int = 4)(implicit p: Paramete
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (in, _) = node.in(0)
in.a.ready := Bool(false)
in.b.valid := Bool(false)
in.c.ready := Bool(false)
in.d.valid := Bool(false)
in.e.ready := Bool(false)
in.a.ready := false.B
in.b.valid := false.B
in.c.ready := false.B
in.d.valid := false.B
in.e.ready := false.B
}
}
31 changes: 16 additions & 15 deletions src/main/scala/devices/tilelink/Error.scala
View file
Expand Up @@ -2,7 +2,8 @@

package freechips.rocketchip.devices.tilelink

import Chisel._
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
Expand All @@ -22,7 +23,7 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)
val a = if (buffer) {Queue(in.a, 1)} else in.a

val da = Wire(in.d)
val idle = RegInit(Bool(true))
val idle = RegInit(true.B)

val a_last = edge.last(a)
val (da_first, da_last, _) = edge.firstlast(da)
Expand All @@ -32,12 +33,12 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)
da.valid := a.valid && a_last && idle

da.bits.opcode := TLMessages.adResponse(a.bits.opcode)
da.bits.param := UInt(0) // toT, but error grants must be handled transiently (ie: you don't keep permissions)
da.bits.param := 0.U // toT, but error grants must be handled transiently (ie: you don't keep permissions)
da.bits.size := a.bits.size
da.bits.source := a.bits.source
da.bits.sink := UInt(0)
da.bits.denied := Bool(true)
da.bits.data := UInt(0)
da.bits.sink := 0.U
da.bits.denied := true.B
da.bits.data := 0.U
da.bits.corrupt := edge.hasData(da.bits)

if (params.acquire) {
Expand All @@ -48,21 +49,21 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)
val dc_last = edge.last(dc)

// Only allow one Grant in-flight at a time
when (da.fire() && da.bits.opcode === Grant) { idle := Bool(false) }
when (in.e.fire()) { idle := Bool(true) }
when (da.fire && da.bits.opcode === Grant) { idle := false.B }
when (in.e.fire) { idle := true.B }

c.ready := (dc.ready && dc_last) || !c_last
dc.valid := c.valid && c_last

// ReleaseAck is not allowed to report failure
dc.bits.opcode := ReleaseAck
dc.bits.param := Vec(toB, toN, toN)(c.bits.param)
dc.bits.param := VecInit(toB, toN, toN)(c.bits.param)
dc.bits.size := c.bits.size
dc.bits.source := c.bits.source
dc.bits.sink := UInt(0)
dc.bits.denied := Bool(false)
dc.bits.data := UInt(0)
dc.bits.corrupt := Bool(false)
dc.bits.sink := 0.U
dc.bits.denied := false.B
dc.bits.data := 0.U
dc.bits.corrupt := false.B

// Combine response channels
TLArbiter.lowest(edge, in.d, dc, da)
Expand All @@ -71,9 +72,9 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)
}

// We never probe or issue B requests
in.b.valid := Bool(false)
in.b.valid := false.B

// Sink GrantAcks
in.e.ready := Bool(true)
in.e.ready := true.B
}
}
25 changes: 13 additions & 12 deletions src/main/scala/devices/tilelink/MaskROM.scala
View file
Expand Up @@ -2,7 +2,8 @@

package freechips.rocketchip.devices.tilelink

import Chisel._
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation}
Expand All @@ -29,32 +30,32 @@ class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {

val rom = ROMGenerator(ROMConfig(c.name, c.depth, c.width))
rom.io.clock := clock
rom.io.address := edge.addr_hi(in.a.bits.address - UInt(c.address))(log2Ceil(c.depth)-1, 0)
rom.io.oe := Bool(true) // active high tri state enable
rom.io.me := in.a.fire()
rom.io.address := edge.addr_hi(in.a.bits.address - c.address.U)(log2Ceil(c.depth)-1, 0)
rom.io.oe := true.B // active high tri state enable
rom.io.me := in.a.fire

val d_full = RegInit(Bool(false))
val d_full = RegInit(false.B)
val d_size = Reg(UInt())
val d_source = Reg(UInt())
val d_data = rom.io.q holdUnless RegNext(in.a.fire())
val d_data = rom.io.q holdUnless RegNext(in.a.fire)

// Flow control
when (in.d.fire()) { d_full := Bool(false) }
when (in.a.fire()) { d_full := Bool(true) }
when (in.d.fire) { d_full := false.B }
when (in.a.fire) { d_full := true.B }
in.d.valid := d_full
in.a.ready := in.d.ready || !d_full

when (in.a.fire()) {
when (in.a.fire) {
d_size := in.a.bits.size
d_source := in.a.bits.source
}

in.d.bits := edge.AccessAck(d_source, d_size, d_data)

// Tie off unused channels
in.b.valid := Bool(false)
in.c.ready := Bool(true)
in.e.ready := Bool(true)
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}

Expand Down
34 changes: 17 additions & 17 deletions src/main/scala/devices/tilelink/MasterMux.scala
View file
Expand Up @@ -2,7 +2,7 @@

package freechips.rocketchip.devices.tilelink

import Chisel._
import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
Expand All @@ -28,11 +28,11 @@ class MuteMaster(name: String = "MuteMaster", maxProbe: Int = 0)(implicit p: Par
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val Seq((out, edgeOut)) = node.out
out.a.valid := Bool(false)
out.a.valid := false.B
out.b.ready := out.c.ready
out.c.valid := out.b.valid
out.d.ready := Bool(true)
out.e.valid := Bool(false)
out.d.ready := true.B
out.e.valid := false.B

out.c.bits := edgeOut.ProbeAck(out.b.bits, TLPermissions.NtoN)
}
Expand All @@ -45,8 +45,8 @@ class MasterMux(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(impl
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val bypass = Bool(INPUT)
val pending = Bool(OUTPUT)
val bypass = Input(Bool())
val pending = Output(Bool())
})

val Seq((in0, edgeIn0), (in1, edgeIn1)) = node.in
Expand All @@ -57,7 +57,7 @@ class MasterMux(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(impl
val (flight, next_flight) = edgeOut.inFlight(out)

io.pending := (flight > 0.U)
when (next_flight === UInt(0)) { bypass := io.bypass }
when (next_flight === 0.U) { bypass := io.bypass }
val stall = (bypass =/= io.bypass) && edgeOut.first(out.a)

in0.a.ready := !stall && out.a.ready && bypass
Expand Down Expand Up @@ -91,17 +91,17 @@ class MasterMux(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(impl
def castE(x: TLBundleE) = { val ret = Wire(out.e.bits); ret <> x; ret }
out.e.bits := Mux(bypass, castE(in0.e.bits), castE(in1.e.bits))
} else {
in0.b.valid := Bool(false)
in0.c.ready := Bool(true)
in0.e.ready := Bool(true)
in0.b.valid := false.B
in0.c.ready := true.B
in0.e.ready := true.B

in1.b.valid := Bool(false)
in1.c.ready := Bool(true)
in1.e.ready := Bool(true)
in1.b.valid := false.B
in1.c.ready := true.B
in1.e.ready := true.B

out.b.ready := Bool(true)
out.c.valid := Bool(false)
out.e.valid := Bool(false)
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
Expand All @@ -124,7 +124,7 @@ class TLMasterMuxTester(txns: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz1.module.io.finished && fuzz2.module.io.finished
mux.module.io.bypass := LFSR64(Bool(true))(0)
mux.module.io.bypass := LFSR64(true.B)(0)
}
}

Expand Down

0 comments on commit 1ff0db3

Please sign in to comment.