Bump Chisel along 3.4.x release branch

chipsalliance · Nov 2, 2020 · 4e75304 · 4e75304
1 parent 1b9b97b
commit 4e75304
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/build.sbt b/build.sbt
@@ -6,7 +6,7 @@ import scala.sys.process._
 enablePlugins(PackPlugin)
 
 // This needs to stay in sync with the chisel3 and firrtl git submodules
-val chiselVersion = "3.4.0-RC3"
+val chiselVersion = "3.4.0"
 
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",

diff --git a/chisel3 b/chisel3
diff --git a/wit-manifest.json b/wit-manifest.json
@@ -10,7 +10,7 @@
         "source": "git@github.com:sifive/api-chisel3-sifive.git"
     },
     {
-        "commit": "d033d4123672b07a90afb5536b3e6cf83b7228ff",
+        "commit": "8106f183e9c832593edfa218148131e7f0083a6e",
         "name": "chisel3",
         "source": "git@github.com:freechipsproject/chisel3.git"
     },