Avoid structural hazard-induced nacks on external fpu reqs

chipsalliance · Mar 30, 2024 · 8ff7929 · 8ff7929
1 parent 80ff66a
commit 8ff7929
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
@@ -979,7 +979,8 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
     io.cp_resp.bits.data := wdata
     io.cp_resp.valid := true.B
   }
-  io.cp_req.ready := !ex_reg_valid
+  // Avoid structural hazards and nacking of external requests
+  io.cp_req.ready := !ex_reg_valid && !mem_reg_valid && !wb_reg_valid
 
   val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
   val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)