Bump Chisel along 3.4.x release branch

chipsalliance · Nov 6, 2020 · bcd6e69 · bcd6e69
1 parent 449f53d
commit bcd6e69
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Showing 4 changed files with 5 additions and 5 deletions.
diff --git a/build.sbt b/build.sbt
@@ -6,7 +6,7 @@ import scala.sys.process._
 enablePlugins(PackPlugin)
 
 // This needs to stay in sync with the chisel3 and firrtl git submodules
-val chiselVersion = "3.4.0-RC3"
+val chiselVersion = "3.4.0"
 
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",

diff --git a/chisel3 b/chisel3
diff --git a/firrtl b/firrtl
diff --git a/wit-manifest.json b/wit-manifest.json
@@ -10,12 +10,12 @@
         "source": "git@github.com:sifive/api-chisel3-sifive.git"
     },
     {
-        "commit": "d033d4123672b07a90afb5536b3e6cf83b7228ff",
+        "commit": "d379dca4413d4cb08b02165a493faff01f3ddbb9",
         "name": "chisel3",
         "source": "git@github.com:freechipsproject/chisel3.git"
     },
     {
-        "commit": "4f92b94e0e8f35accb4fcc2f06390486d7144740",
+        "commit": "05d047a9befda3877f5d8a0a9e1076ffd520ddf9",
         "name": "firrtl",
         "source": "git@github.com:freechipsproject/firrtl.git"
     },