Merge pull request #3590 from chipsalliance/tracegen-fix

chipsalliance · Mar 16, 2024 · f228714 · f228714
2 parents a721154 + e81ed19
commit f228714
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala
@@ -533,6 +533,7 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
   io.mem.req.bits.tag  := reqTag
   io.mem.req.bits.no_alloc := false.B
   io.mem.req.bits.no_xcpt := false.B
+  io.mem.req.bits.no_resp := false.B
   io.mem.req.bits.mask := ~(0.U((numBitsInWord / 8).W))
   io.mem.req.bits.phys := false.B
   io.mem.req.bits.dprv := PRV.M.U